Granted Patent
Utility
US 5,966,028 · App. 08/929,654
Programming architecture for a programmable integrated circuit employing test antifuses and test transistors
Inventor:
James M. Apland
Patented Case
View Patent ↗
Granted: Oct 12, 1999
Filed: Sep 17, 1997
Inventor
James M. Apland
Assignee (at issue)
QuickLogic Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.