Granted Patent
Utility
US 6,122,724 · App. 09/250,922
Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation
Inventors:
Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
Patented Case
View Patent ↗
Granted: Sep 19, 2000
Filed: Feb 16, 1999
Inventors
Shumpei Kawasaki
Eiji Sakakibara
Kaoru Fukada
Takanaga Yamazaki
Yasushi Akao
Shiro Baba
Toshimasa Kihara
Keiichi Kurakazu
Takashi Tsukamoto
Shigeki Masumura
Yasuhiro Tawara
Yugo Kashiwagi
Shuya Fujita
Katsuhiko Ishida
Noriko Sawa
Yoichi Asano
Hideaki Chaki
Tadahiko Sugawara
Masahiro Kainaga
Kouki Noguchi
Mitsuru Watabe
Assignee (at issue)
HITACHI, LTD.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.