Granted Patent
Utility
US 6,125,462 · App. 09/030,909
Testing mechanism in a semiconductor integrated circuit device using an external clock signal and a non-connection pin input signal
Inventor:
Fumihiko Sato
Patented Case
View Patent ↗
Granted: Sep 26, 2000
Filed: Feb 26, 1998
Inventor
Fumihiko Sato
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.