Granted Patent
Utility
US 6,128,678 · App. 09/143,355
FIFO using asynchronous logic to interface between clocked logic circuits
Inventor:
Steven Robert Masteller
Patented Case
View Patent ↗
Granted: Oct 3, 2000
Filed: Aug 28, 1998
Inventor
Steven Robert Masteller
Assignee (at issue)
Theseus Logic Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.