IP Library › Granted Patent US 6,128,711
Granted Patent Utility
US 6,128,711 · App. 08/745,553

Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writes

Inventors: Samuel H. Duncan, Glenn Arthur Herdeg, Ricky C. Hetherington, Craig D. Keefer, Maurice B. Steinman, Paul Michael Guglielmi
Patented Case View Patent ↗
Granted: Oct 3, 2000 Filed: Nov 12, 1996
Inventors
Samuel H. Duncan
Glenn Arthur Herdeg
Ricky C. Hetherington
Craig D. Keefer
Maurice B. Steinman
Paul Michael Guglielmi
Assignee (at issue)
Compaq Computer Corporation

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Quick Facts
Patent No.
US 6,128,711
App. No.
08/745,553
Filed
1996-11-12
Granted
2000-10-03
Kind
A