Granted Patent
Utility
US 6,218,695 · App. 09/340,979
Area efficient column select circuitry for 2-bit non-volatile memory cells
Inventor:
Ishai Nachumovsky
Patented Case
View Patent ↗
Granted: Apr 17, 2001
Filed: Jun 28, 1999
Inventor
Ishai Nachumovsky
Assignee (at issue)
TOWER PARTNERS SEMICONDUCTOR CO., LTD.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.