Granted Patent
Utility
US 6,442,075 · App. 09/897,999
Erasing method for nonvolatile semiconductor memory device capable of improving a threshold voltage distribution
Inventor:
Yasuaki Hirano
Patented Case
View Patent ↗
Granted: Aug 27, 2002
Filed: Jul 5, 2001
Inventor
Yasuaki Hirano
Assignee (at issue)
SHARP KABUSHIKI KAISHA
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.