Granted Patent
Utility
US 6,492,189 · App. 09/696,196
Method of arranging exposed areas including a limited number of test element group (TEG) regions on a semiconductor wafer
Inventor:
Takahisa Yamaguchi
Patented Case
View Patent ↗
Granted: Dec 10, 2002
Filed: Oct 26, 2000
Inventor
Takahisa Yamaguchi
Assignee (at issue)
Kawasaki Microelectronics, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.