Granted Patent
Utility
US 6,617,669 · App. 10/281,236
Multilayer semiconductor wiring structure with reduced alignment mark area
Inventor:
Hirofumi Saito
Patented Case
View Patent ↗
Granted: Sep 9, 2003
Filed: Oct 28, 2002
Inventor
Hirofumi Saito
Assignee (at issue)
NEC Electronics Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.