Granted Patent
Utility
US 6,625,772 · App. 09/486,943
Circuit arrangement and method for minimizing bit errors
Inventor:
Detlef Stoll
Patented Case
View Patent ↗
Granted: Sep 23, 2003
Filed: Mar 2, 2000
Inventor
Detlef Stoll
Assignee (at issue)
Siemens Aktiengesellschaft
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.