Granted Patent
Utility
US 6,651,235 · App. 10/003,595
Scalable, partitioning integrated circuit layout system
Inventors:
Wei-Jin Dai, Kit Lam Cheong, Hsi-Chuan Chen, Wei-Lun Kao
Patented Case
View Patent ↗
Granted: Nov 18, 2003
Filed: Oct 30, 2001
Inventors
Wei-Jin Dai
Kit Lam Cheong
Hsi-Chuan Chen
Wei-Lun Kao
Assignee (at issue)
Cadence Design Systems, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.