Granted Patent
Utility
US 6,657,485 · App. 10/137,298
Linear voltage subtractor/adder circuit and MOS differential amplifier circuit therefor
Inventor:
Katsuji Kimura
Patented Case
View Patent ↗
Granted: Dec 2, 2003
Filed: May 3, 2002
Inventor
Katsuji Kimura
Assignee (at issue)
NEC Electronics Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.