Granted Patent
Utility
US 6,751,786 · App. 10/043,458
Clock tree synthesis for a hierarchically partitioned IC layout
Inventors:
Chin-Chi Teng, Wei-Jin Dai
Patented Case
View Patent ↗
Granted: Jun 15, 2004
Filed: Jan 9, 2002
Inventors
Chin-Chi Teng
Wei-Jin Dai
Assignee (at issue)
Cadence Design Systems, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.