Chip resistor
A chip resistor having a highly accurately adjusted low resistance value is obtained. The chip resistor having a vertically three-layered structure is obtained by forming a first electrode 1 A by printing paste for an electrode on an insulating substrate 5 and drying it, a resistor layer 3 by printing paste for a resistor on the first electrode 1 A and drying it, a second electrode 1 B by printing paste for an electrode on the resistor layer 3 and the insulating substrate 5 and baking it. Trimming is applied to the thus fabricated chip resistor so as to adjust a resistance value to a given value.
1. A chip resistor comprising:
a first surface electrode formed on an insulating substrate and serving as a first contact electrode;
a resistor layer formed on the first surface electrode;
a second surface electrode formed on the resistor layer and the insulating substrate and serving as a second contact electrode; and
means for adjusting resistance value, said means comprising a cut to at least one of said first surface electrode and said substrate,
wherein a portion of all of said first surface electrode, said second surface electrode and said resistor layer are overlapping on a portion of said insulating substrate.
2. A chip resistor comprising:
a first surface electrode formed on an insulating substrate;
a resistor layer formed on the first surface electrode;
a second surface electrode formed on the resistor layer and the insulating substrate; and
resistance value adjusting means, wherein the resistance value adjusting means comprises a trimming section formed on the resistor layer by trimming the resistor layer through the second surface electrode to at least one of said first surface electrode and said substrate.
3. A chip resistor comprising:
a first surface electrode formed on an insulating substrate;
a resistor layer formed on the first surface electrode;
a second surface electrode formed on the resistor layer and the insulating substrate; and
resistance value adjusting means, wherein the resistance value adjusting means comprises a first trimming section formed on the resistor layer by trimming the resistor layer through the second surface electrode to at least one of said first surface electrode and said substrate, and a second trimming section formed on the resistor layer by trimming the resistor layer at an exposed portion through a cut portion of the second surface electrode to at least one of said first surface electrode and said substrate.
4. A chip resistor according to claim 1 , wherein the second surface electrode is formed on a substantial portion of the surface of the resistor layer and a portion of the insulating substrate.
5. A chip resistor comprising:
an insulating substrate having a planar surface;
a first surface electrode layer formed on said planar surface of said insulating substrate and serving as a first contact electrode;
a resistor layer formed on said first surface electrode layer;
a second surface electrode layer formed on the resistor layer and the insulating substrate and serving as a second electrode contact, wherein a portion of all of said first surface electrode layer, said resistor layer and said second surface electrode layer are overlapping in that order where said first surface layer is formed on a portion of said planar surface; and
a trimming section comprising at least one selectively removed volume of said resistor layer to at least one of said first surface electrode and said substrate, and being operative to adjust the resistance value of the chip resistor.
6. A chip resistor according to claim 5 , wherein the second surface electrode layer is formed on a portion of the surface of the resistor layer and a portion of the insulating substrate.
7. A chip resistor comprising:
an insulating substrate;
a first surface electrode layer formed on said insulating substrate;
a resistor layer formed on said first surface electrode layer;
a second surface electrode layer formed on the resistor layer and the insulating substrate; and
a trimming section comprising at least one selectively removed volume of said resistor layer cut to at least one of said first surface electrode and said substrate and being operative to adjust the resistance value of the chip resistor, wherein the second surface electrode layer comprises an open surface area and said trimming section is disposed under the open surface area of the second surface electrode layer.
8. A chip resistor comprising:
an insulating substrate;
a first surface electrode layer formed on said insulating substrate;
a resistor layer formed on said first electrode layer;
a second surface electrode layer formed on the resistor layer and the insulating substrate; and
a trimming section comprising at least one selectively removed volume of said resistor layer and being operative to adjust the resistance value of the chip resistor, wherein the second surface electrode layer comprises at least a first and a second open surface area separately formed on said second surface electrode layer, and said trimming section has a respective portion that is disposed under each open surface area of the second surface electrode layer formed by a cut to at least one of said first surface electrode and said substrate.
9. The chip resistor according to claim 7 , wherein said open surface area comprises a pre-patterned area.
10. The chip resistor according to claim 7 , wherein said open surface area comprises an etched area.
11. The chip resistor according to claim 7 , wherein said open surface area comprises a cut area.