Semiconductor memory device for storing multivalued data
Before the next data is stored into a first memory cell in which i bits of data have been stored, i or less bits of data are written into cells adjacent to the first memory cell beforehand. The writing of i or less bits of data is done using a threshold voltage lower than the original threshold voltage (or the actual threshold voltage in storing i bits of data). After the adjacent cells have been written into, writing is done to raise the threshold voltage of the first memory cell.
1. A semiconductor memory device comprising:
a memory cell array in which a plurality of memory cells are arranged in a matrix, each storable n-valued data (n is a natural number equal to or larger than 2), each of the memory cells being configured by a nonvolatile memory; and
a write circuit which writes data into each of the memory cells and which, before storing next at least one-valued data into a first memory cell in which j-valued data (j<n) has been stored in the memory cell array, writes j or less-valued data into at least one of the memory cells adjacent to the first memory cell.
2. The semiconductor memory device according to claim 1 , wherein the memory cells constitute a NAND-type memory.
3. The semiconductor memory device according to claim 1 , wherein each of the memory cells is configured by an EEPROM.
4. The semiconductor memory device according to claim 1 , wherein the write circuit, when writing j or less-valued data into at least one of the adjacent memory cells, writes the data at a first threshold voltage lower than that of the original data and, after having written the data into at least one of the adjacent memory cells, writes the data at a second threshold voltage higher than the first threshold voltage.
5. The semiconductor memory device according to claim 4 , wherein the write circuit writes j-valued data in the first memory cell at a second threshold voltage higher than the first threshold voltage simultaneously with the operation of writing next at least one-valued data in the first memory cell.
6. The semiconductor memory device according to claim 1 , wherein the memory cell array includes a second memory cell which acts as a flag and has at least a first and a second logic level.
7. The semiconductor memory device according to claim 6 , wherein the memory cell array, when reading the first memory cell, carries out a read operation suitable for the first threshold voltage in a case where the second memory cell is at the first logic level and carries out a read operation suitable for the second threshold voltage in a case where the second memory cell is at the second logic level.
8. The semiconductor memory device according to claim 6 , wherein the write operation, when writing j-valued data in the first memory cell at the second threshold voltage, writes data into the second memory cell and sets the second memory cell to one of the first and second logic levels.
9. The semiconductor memory device according to claim 6 , wherein the write circuit, when writing (j+1)-valued data into the first memory cell, writes data into the second memory cell and changes the logic level of the second memory cell from the first logic level to the second logic level.
10. The semiconductor memory device according to claim 7 , wherein the write circuit, while writing j-valued data in the first memory cell at the second threshold voltage and writing (j+1)-valued data in the first memory cell, writes data into the second memory cell and changes the logic level from the first logic level to the second logic level.
11. The semiconductor memory device according to claim 7 , wherein the memory cell array includes a plurality of second memory cells selected simultaneously with the first memory cell and, in a write operation, stores data of the same logic level into each of the second memory cells and, in a read operation, determines the first and second logic levels by a majority decision of the data read from said plurality of second memory cells.
12. The semiconductor memory device according to claim 1 , wherein the adjacent memory cells are the memory cells adjacent to the first memory cell along a word line.
13. The semiconductor memory device according to claim 1 , wherein the adjacent memory cells are the memory cells adjacent to the first memory cells along a bit line.
14. A semiconductor memory device comprising:
a memory cell which stores k bits (k is a natural number equal to or larger than 2);
a plurality of storage circuits;
a first storage circuit of the storage circuits, which stores an input data;
a second storage circuit of the storage circuits, which stores the data read from the memory cell or the input data; and
a control circuit which, in a write operation, holds or changes the data in the first storage circuit or the data in the second storage circuit on the basis of the data stored in the memory cell and which, in the middle of a write operation, inputs next write data to the first storage circuit.
15. The semiconductor memory device according to claim 14 , wherein the first storage circuit is connected to a data line.
16. The semiconductor memory device according to claim 14 , wherein the second storage circuit is connected to the first storage circuit and the memory cell, the second storage circuit which outputs a signal indicating end of a verify operation.
17. The semiconductor memory device according to claim 14 , wherein the storage circuits include a third storage circuit which is connected to the memory cell, the first storage circuit and the second storage circuit, the third storage circuit which stores data from the memory cell.
18. The semiconductor memory device according to claim 14 , wherein the storage circuits include a fourth storage circuit which is connected between the second storage circuit and third storage circuit, the fourth storage circuit which stores data from the second storage circuit.
19. The semiconductor memory device according to claim 14 , wherein the memory cell is configured by an EEPROM.
20. The semiconductor memory device according to claim 18 , wherein the memory cell constitutes a NAND-type memory.
21. A semiconductor memory device comprising:
a memory cell which has a threshold of k-value (k is a natural number equal to or larger than 2);
a first storage circuit which stores an input data from an outside;
a second storage circuit of the storage circuits, which stores data read from the memory cell or the input data; and
a control circuit which writes a threshold of n-value (n is a natural number equal to or smaller than k) into the memory cell according to the data of the first and second storage circuits, and inputs next data from the outside to the first storage circuit when at least one value has written into the memory cell.
22. A semiconductor memory device comprising:
a memory cell which has a threshold of k-value (k is a natural number equal to or larger than 2);
i storage circuits (i is a natural number equal to or larger than 2) store data read from the memory cell or data from an outside; and
a control circuit which writes a threshold of n-value (n is a natural number equal to or smaller than k) into the memory cell according to the data stored in the storage circuits, and inputs next data from the outside to at least one of the storage circuits when at Least one value has written into the memory cell.