Power semiconductor device and method of manufacturing the same
An n-type substrate surface and a p+ region are provided adjacent to each other, on upper surfaces of which an insulation film, a shield and a conductor are formed in this order. The shield is connected to the conductor. The shield and the conductor are insulated from the n-type substrate surface by the insulation film. Even when polarization occurs in a mold provided over a semiconductor device due to a potential distribution along the substrate surface of the semiconductor device, the conductive shield can prevent the substrate from being affected by the polarization in the mold, allowing avoidance of an adverse influence of deterioration in breakdown voltage and the like.
1. A power semiconductor device comprising:
an impurity substrate surface of low concentration having a first conductivity type formed in a predetermined region of a substrate surface;
an impurity region of high concentration having a second conductivity type formed in said substrate surface adjacent to said impurity substrate surface;
a conductor formed over said substrate surface to be insulated from said impurity substrate surface;
a conductive shield formed to include at least part of a region over said impurity substrate surface other than a region where said conductor is formed and to include a region overlapping a boundary region between said impurity substrate surface and said impurity region, said conductive shield being formed over, but not directly contacting, said impurity substrate surface and said impurity region with a predetermined insulation film interposed therebetween, at least part of said conductive shield being connected to said conductor; and
an electrode in contact with said conductive shield and comprised of a different compound than said conductive shield.
2. The power semiconductor device according to claim 1 , further comprising:
a conductive element arranged in the vicinity of said conductive shield leaving a space therebetween and being electrically insulated from said conductive shield; and
another shield formed in the vicinity of said conductive element to be connected to said conductive shield and to be electrically insulated from said conductive element, extending from said boundary region between said impurity substrate surface and said impurity region to said conductive shield.
3. A power semiconductor device, comprising:
a semiconductor element region including a first impurity region of high concentration having a second conductivity type, formed in a substrate surface of a first conductivity type;
a second impurity region of high concentration having said first conductivity type spaced from said semiconductor element region along said substrate surface;
a floating electrode connected to said second impurity region;
one or more third impurity regions of high concentration having said second conductivity type for maintaining breakdown voltage formed in said substrate surface between said first and second impurity regions;
a shielding electrode connected to at least one of said one or more third impurity regions; and
at least one conductive shield formed over and in contact with at least one of: a region interposed between one of said one or more third impurity regions most adjacent to said semiconductor element region and said first impurity region; a region interposed between said one or more third impurity regions; and a region interposed between said second impurity region and one of said one or more third impurity regions most adjacent to said second impurity region, said at least one conductive shield including regions overlapping boundary regions between said first impurity region, said second impurity region and said one or more third impurity regions, with a predetermined insulation film provided between said at least one conductive shield and at least one of said substrate surface, said first impurity region, said one or more third impurity regions and said second impurity region, said at least one conductive shield being connected to said shielding electrode.
4. The power semiconductor device according to claim 3 , wherein
an end of said at least one conductive shield is connected to said shielding electrode adjacent to said end.
5. The power semiconductor device according to claim 3 , wherein
said shielding electrode including a plurality of shielding electrodes, and
said at least one conductive shield is connected to one of said shielding electrodes adjacent to both sides of said at least one conductive shield that has a higher potential.
6. The power semiconductor device according to claim 3 , wherein
said shielding electrode including a plurality of shielding electrodes, and
said at least one conductive shield is connected to one of said shielding electrodes adjacent to both sides of said at least one conductive shield that has a lower potential.
7. The power semiconductor device according to claim 3 , further comprising:
a predetermined semiconductor member electrically insulated from said at least one conductive shield; and
a plurality of conductive members connected to said at least one conductive shield and formed to cover a region between said semiconductor member and said at least one conductive shield.
8. The power semiconductor device according to claim 3 , wherein
said at least one conductive shield is connected to a terminal of said semiconductor element region.
9. The power semiconductor device according to claim 1 , further comprising
a high-insulative passivation film for surface protection formed at least on an upper surface of said at least one conductive shield.
10. The power semiconductor device according to claim 9 , further comprising
a polysilicon element serving as a high-resistive impurity region of low concentration formed in the vicinity of said passivation film.
11. The power semiconductor device according to claim 9 , wherein
said at least one conductive shield can have a potential distribution therein and is connected to electrodes having different potentials from each other, respectively, at a plurality of positions spaced from each other.
12. The power semiconductor device according to claim 3 , further comprising:
a high-insulative passivation film for surface protection formed at least on an upper surface of said at least one conductive shield; and
a polysilicon element serving as a high-resistive impurity region of low concentration formed in the vicinity of said passivation film, wherein
said at least one conductive shield can have a potential distribution therein and is connected to two of said plurality of shielding electrodes adjacent on both sides having different potentials from each other.
13. The power semiconductor device according to claim 11 or claim 12 , wherein
said at least one conductive shield is selected from the group consisting of a shield formed of reverse-biased diode.
14. The power semiconductor device according to claim 11 or claim 12 , wherein
said at least one conductive shield is selected from the group consisting of a shield formed of high-resistive resistor.
15. A power semiconductor device comprising:
an impurity substrate surface of low concentration having a first conductivity type formed in a predetermined region of a substrate surface;
an impurity region of high concentration having a second conductivity type formed in said substrate surface adjacent to said impurity substrate surface;
an insulation film formed on upper surfaces of said impurity substrate surface and said impurity region;
a shield formed on an upper surface of said insulation film, extending from a region over at least part of said impurity substrate surface to a region over a junction of said impurity substrate surface and said impurity region;
a high-potential region formed on part of an upper surface of said shield; and
at least one slit region of high concentration having said second conductivity type formed in said substrate surface under said high-potential region to be spaced and electrically separated from a junction of said impurity substrate surface and said impurity region along said substrate surface.
16. The power semiconductor device according to claim 15 , further comprising:
a plurality of impurity regions of high concentration having said second conductivity type formed in said substrate surface intermittently along said substrate surface such that a potential gradient can be generated along said substrate surface; and
a multistage-coupled Zener diode provided along said potential gradient, wherein
said at least one slit region is electrically separated from said impurity regions and provided in parallel to part of said impurity regions and only under said Zener diode.
17. The power semiconductor device according to claim 16 , wherein
said impurity regions are guard rings provided almost annularly around a predetermined semiconductor element along said substrate surface, and
said at least one slit region is provided on an outer peripheral side with respect to said guard rings.
18. A power semiconductor device, comprising:
an impurity substrate surface of low concentration having a first conductivity type formed in a predetermined region of a substrate surface;
a predetermined semiconductor element formed in part of said substrate surface;
a plurality of guard rings of almost annular shape serving as impurity regions of high concentration having a second conductivity type formed intermittently along said substrate surface such that a potential gradient can be generated along said substrate surface and centered at said predetermined semiconductor element;
an insulation film formed on upper surfaces of said impurity substrate surface and said plurality of guard rings;
a predetermined semiconductor member formed on an upper surface of said insulation film, extending from a region over at least part of said impurity substrate surface to a region over a junction of said impurity substrate surface and said impurity region; and
a high-potential region formed on part of an upper surface of said predetermined semiconductor member on an outer peripheral side with respect to an outermost one of said plurality of guard rings, wherein
when said insulation film has a thickness T, an outermost peripheral position of said outermost one of said plurality of guard rings is determined such that a difference between a potential in said outermost peripheral position and that of said high-potential region provided thereover is not greater than a value Vx obtained by the following equation:
Vx =72.3 ×T +77.6.
19. The power semiconductor device according to claim 18 , wherein
said outermost peripheral position of said outermost one of said plurality of guard rings is determined such that said potential of said high-potential region provided over said outermost one of said plurality of guard rings is not greater than said value Vx.
20. A power semiconductor device, comprising:
a semiconductor element region including a first impurity region of high concentration having a second conductivity type, formed in a substrate surface of a first conductivity type;
a second impurity region of high concentration having said first conductivity type spaced from said semiconductor element region along said substrate surface;
a floating electrode connected to said second impurity region; and
at least one conductive shield formed over a region interposed between said first and second impurity regions and formed to include a region overlapping a region spanning between said first and second impurity regions in said substrate surface, said at least one conductive shield being formed over said substrate surface and said first and second impurity regions with a predetermined insulation film interposed therebetween and being connected to said floating electrode or said terminal.
21. A power semiconductor device comprising:
an impurity substrate surface of low concentration having a first conductivity type formed in a predetermined region of a substrate surface;
an impurity region of high concentration having a second conductivity type formed in said substrate surface adjacent to said impurity substrate surface;
a conductor formed over said substrate surface to be insulated from said impurity substrate surface; and
a conductive shield formed to include at least part of a region over said impurity substrate surface other than a region where said conductor is formed and to include a region overlapping a boundary region between said impurity substrate surface and said impurity region, said conductive shield being formed over said impurity substrate surface and said impurity region with a predetermined insulation film interposed therebetween, at least part of said conductive shield being connected to said conductor.
22. The power semiconductor device according to claim 21 , further comprising:
a conductive element arranged in the vicinity of said conductive shield leaving a space therebetween and being electrically insulated from said conductive shield; and
another shield formed in the vicinity of said conductive element to be connected to said conductive shield and to be electrically insulated from said conductive element, extending from said boundary region between said impurity substrate surface and said impurity region to said conductive shield.
23. The power semiconductor device according to claim 21 , further comprising
a high-insulative passivation film for surface protection formed at least on an upper surface of said at least one conductive shield.
24. A power semiconductor device comprising:
an impurity substrate surface of low concentration having a first conductivity type formed in a predetermined region of a substrate surface;
an impurity region of high concentration having a second conductivity type formed in said substrate surface adjacent to said impurity substrate surface;
a conductor formed over said substrate surface to be insulated from said impurity substrate surface;
a conductive shield formed to include at least part of a region over said impurity substrate surface other than a region where said conductor is formed and to include a region overlapping a boundary region between said impurity substrate surface and said impurity region, said conductive shield being formed over, but not directly contacting, said impurity substrate surface and said impurity region with only a predetermined insulation film interposed between said conductive shield and said substrate surface, at least part of said conductive shield being connected to said conductor; and
an electrode in contact with said conductive shield and comprised of a different compound than said conductive shield.
25. The power semiconductor device according to claim 24 , further comprising:
a conductive element arranged in the vicinity of said conductive shield leaving a space therebetween and being electrically insulated from said conductive shield; and
another shield formed in the vicinity of said conductive element to be connected to said conductive shield and to be electrically insulated from said conductive element, extending from said boundary region between said impurity substrate surface and said impurity region to said conductive shield.
26. The power semiconductor device according to claim 24 , further comprising
a high-insulative passivation film for surface protection formed at least on an upper surface of said at least one conductive shield.