Method and apparatus for integrating flash EPROM and SRAM cells on a common substrate
A system for and a method of integrating SRAM cells and flash EPROM cells onto a single silicon substrate includes an area on the silicon substrate where a local oxidation of silicon (LOCOS) isolation technique is implemented and another area on the same silicon substrate where a shallow trench isolation (STI) technique is implemented. Further, this system and method also include flash EPROM cells implemented within the area of the substrate utilizing the LOCOS isolation technique and SRAM cells implemented within the area of the substrate utilizing the STI technique. Preferably, the LOCOS isolation technique is first implemented to define a flash area of the silicon substrate on which the flash EPROM cell is implemented. Before the LOCOS isolation technique is implemented, an SRAM area is masked. After the LOCOS isolation technique has been fully implemented, the flash area is then preferably masked and the STI technique is implemented in order to define the SRAM area of the silicon substrate on which the SRAM cell is implemented. After the STI technique is implemented, the flash EPROM and the SRAM cells are preferably formed. Thus, the SRAM cells and the flash EPROM cells are both implemented on the common silicon substrate, but yet are appropriately isolated from each other, as well as from other additional devices which may be further implemented on the same silicon substrate, while providing the advantages of respective isolation schemes for the two cells.
1. A semiconductor device comprising:
a common substrate;
an SRAM device implemented on the common substrate and isolated by an STI isolation structure; and
a flash EPROM device implemented on the common substrate and isolated by a LOCOS isolation structure,
wherein the STI isolation structure and the LOCOS isolation structure are implemented non-concurrently.
2. The semiconductor device according to claim 1 wherein the SRAM device is coupled to the flash EPROM device for transmitting signals between the SRAM device and the flash EPROM device.
3. A system containing different types of isolation structures, the system comprising:
a common substrate having a first portion including an STI isolation structure and a second portion including a LOCOS isolation structure, wherein the STI isolation structure and the LOCOS isolation structure are implemented non-concurrently;
an SRAM device on the first portion of the substrate; and
a flash EPROM device on the second portion of the substrate.
4. The system according to claim 3 wherein the SRAM device is coupled to the flash EPROM device for transmitting signals between the SRAM device and the flash EPROM device.
5. A semiconductor device comprising:
a common substrate having a first portion including an STI isolation structure and a second portion including a LOCOS isolation structure, wherein the STI isolation structure and the LOCOS isolation structure are implemented non-concurrently;
an SRAM device implemented on the first portion of the substrate; and
a flash EPROM device implemented on the second portion of the substrate.
6. The semiconductor device according to claim 5 wherein the SRAM device is coupled to the flash EPROM device for transmitting signals between the SRAM device and the flash EPROM device.
7. A semiconductor device, comprising:
a common substrate;
a first portion formed on the common substrate, the first portion comprising an SRAM device over a first single device layer, the first single device layer comprising a first active region and an STI isolation structure; and
a second portion formed on the common substrate, the second portion comprising a flash EPROM device over a second single device layer, the second single device layer comprising a second active region and a LOCOS isolation structure.
8. The semiconductor device of claim 7 , wherein the first single device layer comprises an insulating oxide.
9. The semiconductor device of claim 7 , wherein the second single device layer comprises an insulating oxide.
10. A semiconductor device comprising:
a common substrate;
an SRAM device implemented on the common substrate and formed over a first active region on a first isolated structure including an STI isolation structure; and
a flash EPROM device implemented on the common substrate and formed over a second active region on a second isolated structure including a LOCOS isolation structure, the second isolated structure having an outer portion extending a first depth into the substrate and an inner portion including the second active region and extending a second depth into the substrate, the first depth larger than the second depth.
11. The semiconductor device of claim 10 , wherein the first isolated structure and the second isolated structure are contiguous.
12. The semiconductor device of claim 10 , wherein the first isolated structure and the second isolated structure both comprise an oxide material.
13. A system containing a semiconductor device having a plurality of isolated structures, the system comprising:
a common substrate having a first area including an STI isolation structure and a second area including a LOCOS isolation structure, the second area having an outer portion extending a first depth into the substrate and an inner portion including an active region extending a second depth into the substrate, wherein the first depth is larger than the second depth;
an SRAM device implemented on the first area of the substrate; and
a flash EPROM device implemented on the second area of the substrate.
14. The system of claim 13 , wherein the first area and the second area are contiguous.
15. The system of claim 14 , wherein the first area and the second area both comprise an oxide material.