Non-volatile semiconductor memory device with a memory unit including not more than two memory cell transistors
A semiconductor integrated circuit device includes a semiconductor substrate, an element isolation region, a first interconnection, a second interconnection, and a memory cell unit connected between a corresponding one of the first interconnection and a second interconnection. The memory cell unit includes two selection transistors and memory cell transistors of not larger than two. The memory cell transistors are connected between the two selection transistors. The memory cell transistor has a charge storage layer whose side surface lies in the same plane as the side surface of the element isolation regions.
1. A semiconductor integrated circuit device comprising:
a semiconductor substrate;
an element isolation region formed on the semiconductor substrate to separately define an element active region on the semiconductor substrate;
a first interconnection;
a second interconnection; and
a memory cell unit formed in the element active region and connect between the first interconnection and the second interconnection, the memory cell unit including two selection transistors and memory cell transistors of not larger than two which are connected between the two selection transistors, the memory cell transistors having a charge storage layer whose side surface lies in the same plane as a side surface of the element isolation region.
2. The device according to claim 1 , wherein the memory cell unit is an AND memory cell unit.
3. The device according to claim 1 , wherein one end of the current path of the selection transistor and the first interconnection or the second interconnection is connected together via a contact which is formed to partly cover a portion above a gate electrode of the selection transistor.
4. The device according to claim 1 , wherein a gate electrode of the selection transistor includes a first conductive layer and a second conductive layer which is short-circuited to the first conductive layer.
5. The device according to claim 1 , wherein an impurity concentration of a channel of the selection transistor is higher than that of the memory cell transistor.
6. The device according to claim 1 , wherein the first interconnection is arranged above the second interconnection and connected to a source/drain diffusion layer of one of the two selection transistors via a contact formed to extend from a layer in which the first interconnection is formed and directly formed on the above source/drain diffusion layer, and the second interconnection is connected to a source/drain diffusion layer of the other of the two selection transistors via a contact formed to extend from a layer in which the second interconnection is formed and directly formed on the above source/drain diffusion layer.
7. The device according to claim 1 , wherein the memory cell unit is an NAND memory cell unit.
8. The device according to claim 4 , wherein the one of the first and second interconnections is a source line and the source line is formed above the gate electrode of the selection transistor.
9. A semiconductor integrated circuit device comprising:
a semiconductor substrate;
an element isolation region formed on the semiconductor substrate to separately define an element active region on the semiconductor substrate;
a first interconnection;
a second interconnection; and
a memory cell unit formed in the element active region and connected between the first interconnection and the second interconnection, the memory cell unit including one selection transistor and one memory cell transistor which make one pair, the memory cell transistor having a charge storage layer whose side surface lies in the same plane as a side surface of the element isolation region.
10. The device according to claim 9 , wherein a gate electrode of the selection transistor includes a first conductive layer and a second conductive layer which is short-circuited to the first conductive layer.
11. The device according to claim 9 , wherein an impurity concentration of a channel of the selection transistor is higher than that of the memory cell transistor.
12. The device according to claim 9 , wherein the first interconnection is arranged above the second interconnection and connected to a source/drain diffusion layer of one of the two selection transistors via a contact formed to extend from a layer in which the first interconnection is formed and directly formed on the above source/drain diffusion layer, and the second interconnection is connected to a source/drain diffusion layer of the other of the two selection transistors via a contact formed to extend from a layer in which the second interconnection is formed and directly formed on the above source/drain diffusion layer.
13. The device according to claim 9 , wherein the memory cell unit is an NAND memory cell.
14. The device according to claim 9 , wherein the memory cell unit is an AND memory cell unit.
15. The device according to claim 9 , wherein one end of the current path of the selection transistor and the first interconnection or the second interconnection is connected together via a contact which is formed to partly cover a portion above a gate electrode of the selection transistor.
16. The device according to claim 10 , wherein the one of the first and second interconnections is a source line and the source line is formed above the gate electrode of the selection transistor.