IP Library Granted Patent US 6,933,217
Granted Patent B2
US 6,933,217 · App. 10/274,563 · Granted Aug 23, 2005

Method for forming a ROM coding in a semiconductor device

Assignee: Hynix Semiconductor Inc.
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Quick Facts
Patent No.
US 6,933,217
App. No.
10/274,563
Granted
Aug 23, 2005
Kind
B2
Abstract

Disclosed is a method for manufacturing a semiconductor device. The source/drain impurity area is formed by using the open base characteristic, the ion implantation of high density impurities for connecting source/drain is performed, the first contact hole, the non-crystalline poly-silicon layer and the PMD layer are formed consecutively, the ion implantation is performed, and then the metal lines are formed. Therefore, the size of the chip is reduced as the coding is performed by using the first contact hole without any coding area, the damage to the semiconductor substrate is reduced and the leakage current is reduced as the first contact hole is formed before the PMD layer, the ON characteristic can be achieved by the reverse type ion implantation to the OFF characteristic, which is contrary to the case of a current ROM coding techniques, and the cutting of the metal line is minimized as the poly-silicon layer is formed under the metal line layer during the deposition of the metal lines.

Claims (15)

1. A method for manufacturing a semiconductor device comprises:

depositing a gate oxidation layer on a semiconductor substrate having a lower construction;

forming a first contact hole for connecting elements electrically, by a wet etching of an area to be used as a ROM coding area on the gate oxidation layer;

depositing a doped poly-silicon layer on a result formed with the first contact hole;

forming a gate electrode and a first conductive line by patterning a part of poly-silicon layer to be used as a conductive line;

performing an ion implantation of low-density impurities connecting a source/drain area whereby the source/drain impurity areas are formed on both sides of the gate electrode on the semiconductor substrate;

depositing a nitride layer on an entire surface of the semiconductor substrate and forming nitride spacers at both sides of the gate electrode by etching the nitride layer;

making a part for ROM coding on a result formed with the nitride spacer, and performing an ion implantation of high density impurities on an area other than a ROM coding transistor;

depositing a PMD layer on the resulting structure and forming a second contact hole by a photolithography process;

forming a resist pattern on the result formed with the second contact hole, and forming a ROM coding by ion implantation by using the resist pattern as a mask; and

depositing a metal to be used as a metal line on the result, and forming a second metal line by patterning through a photolithography process.

2. The method for manufacturing a semiconductor device of claim 1 , wherein the depositing of the doped poly-silicon layer on the result formed with the first contact hole further comprises depositing a non-crystalline silicon layer.

3. The method for manufacturing a semiconductor device of claim 1 , wherein an original thickness of the poly-silicon layer used for the first conductive line ranges from about 2000 Å to about 4000 Å.

4. The method for manufacturing a semiconductor device of claim 1 , wherein the step of forming the ROM coding by the ion implantation is performed with an energy ranging from about 50 KeV to about 100 KeV.

5. The method for manufacturing a semiconductor device of claim 3 , wherein the first conductive line is etched to about a tenth of its original thickness during the forming of the second contact hole.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2020
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: KEY FOUNDRY CO., LTD.
Reel/Frame 053703/0227 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY ADDRESS PREVIOUSLY RECORDED AT REEL: 024563 FRAME: 0807. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE BY SECURED PARTY. Recorded Nov 25, 2014
From: US BANK NATIONAL ASSOCIATION
To: MAGNACHIP SEMICONDUCTOR LTD.
Reel/Frame 034469/0001 →
RELEASE OF SECURITY INTEREST Recorded Jun 22, 2010
From: U.S. BANK NATIONAL ASSOCIATION
To: MAGNACHIP SEMICONDUCTOR LTD.
Reel/Frame 024563/0807 →
AFTER-ACQUIRED INTELLECTUAL PROPERTY KUN-PLEDGE AGREEMENT Recorded Feb 18, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
Reel/Frame 022277/0133 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2005
From: HYNIX SEMICONDUCTOR, INC.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 016216/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 24, 2002
From: KO, JU-WAN
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 013605/0982 →
Priority Claims (1)
KR 2001-65106 · Oct 22, 2001 · national
Continuity (1)
Related Publication 20030077889A1 · Apr 24, 2003