Semiconductor memory device with reduced data access time
A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.
1. A memory device, comprising;
at least two cell blocks connected to a global bit line for outputting data in response to an instruction;
at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and
said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.
2. The memory device as recited in claim 1 , wherein each cell block includes;
a first cell array including a plurality of unit cells and outputting data;
a first bit line sense amplifier block for amplifying data outputted from the first cell array and outputting the amplified data to the global bit line; and
a first bit line sense amplifier connection unit for connecting the first cell array to the first bit line sense amplifier block and disconnecting the first cell array to the first bit line sense amplifier block as soon as the data are sensed in the first bit line sense amplifier block.
3. The memory device as recited in claim 2 , wherein each cell block includes:
a second bit line sense amplifier block for amplifying data inputted from the global bit line; and
a second bit line sense amplifier connection unit for connecting or disconnecting the first cell array to the second bit line sense amplifier block.
4. The memory device as recited in claim 3 , further comprising a latch means for transiently latching the data supplied to the global bit line in response to the instruction.
5. The memory device as recited in claim 4 , wherein the control block controls to restore the data latched by the latch means in the first cell block and to read another data stored in the first cell block or another cell block in response to the next instruction at a substantially simultaneous timing period.
6. The memory device as recited in claim 5 , wherein the control block controls to output the data latched by the latch means in response to the active instruction.