Ferro-electric memory device and method of manufacturing the same
A ferro-electric memory device includes a semiconductor substrate, a first transistor formed on the semiconductor substrate, and a first ferro-electric capacitor electrically connected to the first transistor and formed of a first capacitor material layer having a first lower electrode, a first ferro-electric film, and a first upper electrode, the first ferro-electric capacitor being thicker at its central portion than at its ends.
1. A ferro-electric memory device comprising: a semiconductor substrate;
a first transistor formed on the semiconductor substrate;
a first ferro-electric capacitor electrically connected to the first transistor and formed of a first capacitor material layer having a first lower electrode, a first ferro-electric film, and a first upper electrode, the first ferro-electric capacitor being thicker at its central portion than at its ends; and
a first insulating film formed on the first transistor and the semiconductor substrate and having a groove with curved sides, and wherein the first ferro-electric capacitor is provided in the groove.
2. The ferro-electric memory device according to claim 1 , wherein the first ferro-electric capacitor has a bowl shape with a curved top surface.
3. The ferro-electric memory device according to claim 1 , wherein the first lower electrode is formed of a material having an oxygen diffusion prevention effect.
4. The ferro-electric memory device according to claim 1 , further comprising:
a second transistor formed on the semiconductor substrate; and
a second ferro-electric capacitor electrically connected to the second transistor and formed of a second capacitor material layer having a second lower electrode, a second ferro-electric film, and a second upper electrode, the second ferro-electric capacitor being thicker at its central portion than at its ends, and
wherein a first cell in which the first upper electrode and the first lower electrode are electrically connected in parallel with first sources/drains of the first transistor is electrically connected in series with a second cell in which the second upper electrode and the second lower electrode are electrically connected in parallel with second sources/drains of the second transistor.
5. The ferro-electric memory device according to claim 4 , further comprising:
a first contact provided adjacent to the first upper electrode to electrically connect the first upper electrode and one of the first sources/drains; and
a second contact provided adjacent to the second upper electrode to electrically connect the second upper electrode and one of the second sources/drains.
6. The ferro-electric memory device according to claim 5 , wherein the first upper electrode covers the first lower electrode, and the second upper electrode covers the second lower electrode.