Method for initiating internal parity operations in a CAM device
A circuit and a method of operating the circuit is provided. The method generally comprises the steps of (A) receiving an explicit error checking instruction generated outside the circuit, (B) performing an error checking operation for at least one of a plurality of memory locations within the circuit, and (C) generating a result signal from the error checking operation.
1. A method of operating a circuit, comprising the steps of:
(A) receiving an explicit error checking instruction generated outside said circuit;
(B) performing an error checking operation for at least one of a plurality of memory locations within said circuit;
(C) generating a result signal from said error checking operation; and
(D) completing said error checking operation within a predetermined number of clock cycles.
2. The method according to claim 1 , wherein said step (B) comprises the sub-step of performing said error checking operation on at least two of said memory locations for each said explicit error checking instruction received.
3. The method according to claim 2 , wherein said explicit error checking instruction indicates said at least two memory locations.
4. The method according to claim 1 , wherein said step (B) further comprises the sub-step of performing said error checking operation at a starting address generated outside said circuit.
5. The method according to claim 4 , wherein said explicit error checking instruction comprises said starting address.
6. The method according to claim 4 , further comprising the step of incrementing said starting address by a plurality of address units.
7. The method according to claim 1 , wherein said explicit error checking instruction indicates said predetermined number of clock cycles.
8. The method according to claim 1 , further comprising the step of performing said error checking operation in response to an idle instruction received while a configuration signal is in a first state.
9. The method according to claim 1 , further comprising the step of performing said error checking operation in response to not receiving a valid instruction for a predetermined amount of time while a configuration signal is in a first state.
10. The method according to claim 1 , further comprising the step of disabling said explicit error checking instruction in response to a configuration signal having a first state.
11. A circuit comprising:
a plurality of memory locations;
a checking circuit configured to (i) perform an error checking operation for at least one of said memory locations in response to receiving an explicit error checking instruction generated outside said circuit and (ii) generate a result signal from said error checking operation; and
a register coupled to said memory locations and configured to store an address generated outside said circuit.
12. The circuit according to claim 11 , further comprising a counter configured to increment said address by a plurality of address units.
13. The circuit according to claim 11 , further comprising a control circuit configured to detect said explicit error checking instruction from a stream of instructions.
14. The circuit according to claim 11 , wherein each of said memory locations comprises an error detection portion accessible to said error checking operation.
15. The circuit according to claim 11 , wherein said memory locations are configured as a first content addressable memory circuit.
16. The circuit according to claim 15 , further comprising a second content addressable memory circuit cascaded with said first content addressable memory circuit and responsive to said explicit error checking instruction received by said first content addressable memory circuit.
17. The circuit according to claim 11 , wherein said checking circuit is further configured to perform said error checking operation on all said memory locations in response to receiving a predetermined number of said explicit error checking instructions.
18. A method of operating a circuit, comprising the steps of:
(A) receiving an explicit error checking instruction generated outside said circuit;
(B) performing an error checking operation for at least one of a plurality of memory locations within said circuit;
(C) generating a result signal from said error checking operation; and
(D) disabling said explicit error checking instruction in response to a configuration signal having a first state.