Multi-finger transistor
A multi-finger transistor is described, including multiple parallel transistors. Each transistor includes a gate dielectric layer, a gate, a source/drain region, and a drift region in the peripheral substrate of the source/drain region separating the source/drain region and the channel region under the gate. The width of the drift region extending from the side boundary of the source/drain region increases stepwise from the edge sections of the multi-finger transistor toward the central section of the same.
1. A multi-finger transistor, comprising:
a plurality of parallel gates on a substrate;
a gate dielectric layer between the gates and the substrate;
a plurality of source/drain regions, each source/drain region is formed in the substrate beside each gate, wherein a region in the substrate under each gate is a channel region; and
a plurality of drift regions, each drift region is formed in the substrate between each channel region and each source/drain region, wherein
the drift regions in a central section of the multi-finger transistor surround the corresponding source/drain regions, and a width from a side boundary of the source/drain region to a boundary of the drift region along a direction parallel to the gate increases stepwise from the edge sections of the multi-finger transistor toward the central section of the multi-finger transistor.
2. The multi-finger transistor of claim 1 , wherein the multi-finger transistor is divided into 2m+1 sections along an arrangement direction of the parallel gates, wherein m is a positive integer, and the width is smallest in the outmost sections of the multi-finger transistor and increases therefrom toward the central section of the multi-finger transistor.
3. The multi-finger transistor of claim 2 , wherein m is 1 or 2.
4. The multi-finger transistor of claim 2 , wherein the width is zero in the outmost sections of the multi-finger transistor.
5. The multi-finger transistor of claim 1 , further comprising an isolation layer above each drift region, and each gate partially covers the isolation layer.
6. The multi-finger transistor of claim 5 , wherein the isolation layer comprises a field oxide layer.
7. The multi-finger transistor of claim 1 , wherein the source or drain region beside one of the gate is connected with the source or drain region beside another gate.
8. The multi-finger transistor of claim 7 , wherein a width of the drain region is larger than a width of the source region.
9. A multi-finger transistor, comprising:
a plurality of parallel gates on a substrate, wherein the substrate further has a pick-up region thereon;
a gate dielectric layer between the gates and the substrate;
a plurality of source/drain realons each a source/drain region is formed in the substrate beside each gate, wherein a region in the substrate under each gate is a channel region; and
a plurality of drift regions, each drift region is formed in the substrate between each channel region and each source/drain region,
the drift regions in a central section of the multi-finger transistor surround the corresponding source/drain regions, and a width from a side boundary of the source/drain region to a boundary of the drift region along a direction parallel to the gate increases with an increase in a distance between each gate and the pick-up region.
10. The multi-finger transistor of claim 9 , further comprising an isolation layer above each drift region and each gate partially covers the isolation layer.
11. The multi-finger transistor of claim 10 , wherein the isolation layer comprises a field oxide layer.
12. The multi-finger transistor of claim 9 , wherein the source or drain beside one of the gate is connected with the drain or source beside another gate.
13. The multi-finger transistor of claim 12 , wherein a width of the drain region is larger than a width of the source region.