Reset arrangement for a microcontroller
A reset arrangement for a microcontroller and/or further hardware circuits to be reset should be optimally adaptable to the requirements of the microcontroller and/or the hardware circuits. To this end, the reset arrangement is formed in such a way that it is capable of applying a reset signal to the microcontroller via a reset line, supplies a first reset signal upon a system cold start of the reset arrangement and the microcontroller, the duration of this first reset signal being chosen to be such that any provided type of microcontroller starts reliably, is programmed with a second reset signal after a system cold start of the microcontroller, the duration of this second reset signal being adapted to the requirements of the microcontroller, and supplies the second, programmed reset signal as a reset signal at subsequent cold or hot starts.
1. A reset arrangement for a microcontroller ( 3 ), wherein the reset arrangement
is capable of applying a reset signal to the microcontroller ( 3 ) via a reset line (Res),
supplies a first reset signal (Res 1 ) upon a system cold start of the reset arrangement and the microcontroller ( 3 ), the duration of this first reset signal being chosen to be such that any provided type of microcontroller ( 3 ) starts reliably,
is programmed with a second reset signal (Res 2 ) after a system cold start of the microcontroller ( 3 ), the duration of this second reset signal being adapted to the requirements of the microcontroller ( 3 ), and
supplies the second, programmed reset signal (Res 2 ) as a reset signal at subsequent cold or hot starts.
2. A reset arrangement as claimed in claim 1 , characterized in that the reset arrangement is arranged on a system chip ( 1 ) which also comprises analog components ( 2 ) and components for power supply.
3. A reset arrangement as claimed in claim 1 , characterized in that, the second programmed reset signal (Res 2 ) has a shorter duration than the first reset signal (Res 1 ).
4. A reset arrangement as claimed in claim 1 , characterized in that in the case where a reset of the microcontroller ( 3 ) by means of the second reset signal (Res 2 ) fails upon a cold or a hot start, the reset arrangement subsequently supplies a reset signal corresponding to the first reset signal (Res 1 ).
5. A reset arrangement as claimed in claim 4 , characterized in that, in the case where a reset of the microcontroller by means of the first reset signal (Res 1 ) also fails, the reset arrangement sets the microcontroller to a low-power error mode (LPM 2 ).
6. A reset arrangement as claimed in claim 1 , characterized in that the reset arrangement monitors the reset line after supply of a reset signal and sets the microcontroller ( 3 ) to a low-power error mode (LPM 2 ) in the case where, after the reset, the microcontroller does not release the reset line (Res) after a predetermined period of time, or in the case where the reset line (Res) is clamped at an external potential.
7. A reset arrangement as claimed in claim 1 , characterized in that the reset arrangement is capable of waking up the microcontroller ( 3 ) from a low-power mode (LPM 1 ).
8. A reset arrangement as claimed in claim 5 , characterized in that the reset arrangement wakes up the microcontroller ( 3 ) from a low-power mode (LPM 1 , LPM 2 ) after the occurrence of an internal or external wake-up event.