Chip-size semiconductor package
A chip-size semiconductor package includes a semiconductor chip; a metal pad formed on the semiconductor chip; a conductive wiring pattern electrically connected to the metal pad; a molding resin formed over the conductive wiring pattern; and a terminal member which is electrically connected to the conductive wiring pattern, wherein the conductive wiring pattern comprises a termial portion on which the terminal member is formed, an extended portion extending from the terminal portion and a connecting portion arranged between the terminal portion and the extended portion. The portion connecting portion between the extended portion and the terminal portion is provided with a slit, to disperse stress applied to the connecting portion.
1. A chip-size semiconductor package, comprising:
a semiconductor chip;
a metal pad formed on the semiconductor chip;
a conductive wiring pattern electrically connected to the conductive metal pad;
a molding resin formed over the conductive wiring pattern; and
a terminal member which is electrically connected to the conductive wiring pattern, wherein
the conductive wiring pattern comprises a terminal portion on which the terminal member is formed, an extended portion extending from the terminal portion and a connecting portion arranged between the terminal portion and the extended portion,
the connecting portion has a width that gradually decreases toward the extended portion, and
the connecting portion has a slit to disperse stress to be applied to the connecting portion.
2. A chip-size semiconductor package according to claim 1 , wherein the connecting portion is provided with a plurality of slits, which are separated from each other.
3. A chip-size semiconductor package according to claim 2 , wherein the slits are rectangular shaped and are arranged to extend radially away from each other.
4. A chip-size semiconductor package according to claim 1 , further comprising a wafer coat formed over the semiconductor chip, wherein the conductive wiring pattern is formed on the wafer coat.
5. A chip-size semiconductor package according to claim 1 , wherein the terminal member comprises a conductive post that is arranged on the terminal portion, and a terminal that is formed on the conductive post and exposed from the molding resin.
6. A chip-size semiconductor package, comprising:
a semiconductor chip;
a metal pad formed on the semiconductor chip;
a conductive wiring pattern electrically connected to the metal pad;
a molding resin formed over the conductive wiring pattern; and
a terminal which is electrically connected to the conductive wiring pattern, wherein
the conductive wiring pattern comprises a terminal portion on which the terminal member is formed, an extended portion extending from the terminal portion and a connecting portion arranged between the terminal portion and the extended portion,
the connecting portion has a width that gradually decreases from a first boundary at the terminal portion to a second boundary at the extended portion, and
a dummy pattern arranged adjacent the first and second boundaries and along sides of the connecting portion, the molding resin also being formed on the dummy pattern.
7. A chip-size semiconductor package according to claim 6 , wherein the dummy pattern is a conductive pattern which is formed during a same process as the conductive wiring pattern and is arranged paprallel to the conductive wiring pattern.
8. A chip-size semiconductor package accroding to claim 6 , wherein the dummy pattern comprises two parts respectively arranged along both sides of the connecting portion.
9. A chip-size semiconductor package according to claim 6 , further comprising a wafer coast formed over the semicoductor chip, wherein the conductive wiring pattern is formed on the wafer coat.
10. A chip-size semiconductor package according to claim 6 , wherein the terminal member comprises a conductive post that is arranged on the terminal portion, and a terminal that is formed on the conductive post and exposed from the molding resin.
11. A chip-size semiconductor package, comprising:
a semiconductor chip;
a metal pad formed on the semiconductor chip;
a conductive wiring pattern electrically connected to the metal pad;
a molding resin formed over the conductive wiring pattern; and
a terminal member which is electrically connected to the conductive wiring pattern, wherein
the conductive wiring pattern comprises a terminal portion on which the terminal member is formed, an extended portion extending from the terminal portion and a connecting portion arranged between the terminal portion and the extended poriton.
the connecting portion has a width that gradually decreases from a first boundary at the terminal portion to a second boundary at the extended portion, and
a dent is formed at and around the connecting portion.
12. A chip-size semiconductor package according to claim 11 , wherein the dent is square shaped.
13. A chip-size semiconductor package according to claim 11 , further comprising a wafer coat formed over the semiconductor chip, wherein the conductive wiring pattern is formed on the wafer coat.
14. A chip-size semiconductor package according to claim 11 , wherein the terminal member comprises a conductive post that is arranged on the terminal portion, and a terminal that is formed on the conductive post and exposed from the molding resin.
15. A chip-size semiconductor package, comprising;
a semiconductor chip;
a metal pad formed on the semiconductor chip;
a conductive wiring pattern electrically connected to the metal pad;
a molding resin formed over the conductive wiring pattern; and
a terminal member which is electrically connected to the conductive wiring pattern, wherein
the conductive wiring pattern comprises a terminal portion on which the terminal member is formed, an extended portion extending from the terminal portion and a connecting portion arranged between the terminal portion and the extended poriton,
the connecting portion has a width that gradually decreases from a first boundary at the terminal portion to a second boundary at the extended portion, and
the connecting portion has a first region extending outwardly from the terminal portion and a second region extending in a perpendicular direction from the first region, the second region extending from the connecting portion.
16. A chip-size semiconductor package according to claim 15 , further comprising a plurality of projecting parts each of which extends in the perpendicular direction from the conductive wiring pattern.
17. A chip-size semiconductor package according to claim 16 , wherein the second region extends from both sides of the first region.
18. A chip-size semiconductor package according to claim 15 , further comprising a wafer coat formed over the semiconductor chip, wherein the conductive wiring pattern is formed on the wafer coat.
19. A chip-size semiconductor package according to claim 15 , wherein the terminal member comprises a conductive post that is arranged on the terminal portion, and a terminal that is formed on the conductive post and exposed from the molding resin.