Grid array electronic component, wire reinforcing method for the same, and method of manufacturing the same

1. An electronic component comprising:

a board;

a semiconductor device comprising a plurality of first lands formed in a grid and electrically connected to corresponding second lands formed on the board,

wherein a subset of the second lands corresponding to first lands in a corner portion or end portion of the grid each comprise a primary land and an auxiliary land,

each of the subset of second lands connect to a wire of the board,

the primary land comprises an arcuate shape, and

the auxiliary land comprises a first portion disposed adjacent the primary land and a second portion connecting to the wire, the first portion having a greater cross sectional area than the second portion, and

wherein (a) the connecting wire for each land of the subset of second lands comprises a via land, the via land including an arcuate portion electrically connected to a via hole formed in the board outside of the footprint of the grid of the semiconductor device and (b) a predetermined tensile stress is configured to be applied between the subset of second lands and their respective connecting wires.

2. The electronic component according to claim 1 , wherein said auxiliary land is configured to be disposed where the predetermined tensile stress is applied when a load is applied to said board.

3. The electronic component according to claim 2 , wherein said auxiliary land electrically connects with at least one of the first lands at a corner of the semiconductor device.

4. The electronic component according to claim 3 , wherein said auxiliary land has a shape determined based on a position of the auxiliary land in relation to a corner of the semiconductor device.

5. The electronic component according to claim 3 , wherein said auxiliary land comprises an arcuate shape.

6. The electronic component according to claim 2 , wherein said auxiliary land electrically connects with at least one of the first lands at an end of an integrated circuit of the semiconductor device.

7. The electronic component according to claim 2 , wherein said auxiliary land is configured to be disposed so as to extend in a direction in which a warpage of said board is generated.

8. The electronic component according to claim 2 , wherein said auxiliary land is configured to be disposed where the predetermined tensile stress is applied during correction of a distortion of said board during an assembly of the semiconductor device to the board.

9. The electronic component according to claim 2 , wherein said auxiliary land comprises a third portion disposed between the first and second portions, the third portion having a cross sectional area less than the first portion and greater than the second portion.

10. The electronic component according to claim 2 , wherein the at least one second land comprises a second auxiliary land disposed adjacent a through hole.

11. An electronic component comprising:

a printed wiring board;

a semiconductor device comprising a plurality of first lands formed in a grid and electrically connected to corresponding second lands formed on the printed wiring board,

wherein a subset of the second lands corresponding to first lands in a corner portion or end portion of the grid each comprise a primary land and an auxiliary land,

each of the subset of second lands connects to a wire of the printed wiring board,

the primary land comprises an arcuate shape, and

the auxiliary land comprises a first portion disposed adjacent the primary land and a second portion connecting to the wire, the first portion having a greater cross sectional area than the second portion, and

wherein (a) the connecting wire for each land of the subset of second lands comprises a via land, the via land including an arcuate portion electrically connected to a via hole formed in the printed wiring board outside of the footprint of the grid of the semiconductor device and (b) a predetermined tensile stress is configured to be applied between the subset of second lands and their respective connecting wires.

12. An electronic component, comprising:

a semiconductor device having a footprint, and comprising at least one semiconductor land;

a board comprising at least one board land, each of said at least one semiconductor lands electrically connected to a corresponding board land of the at least one board lands, the corresponding board lands including a primary portion contacting the at least one semiconductor land and an auxiliary portion electrically connected to a wire,

wherein the primary portion comprises an arcuate shape, and

the auxiliary portion comprises a first portion electrically connected to the primary portion and a second portion electrically connected to the wire, the first portion having a greater cross sectional area than the second portion, and

wherein the wire for each corresponding board land comprises a via land, the via land including an arcuate portion electrically connected to a via hole formed in the board outside of the footprint of the semiconductor device.

13. The electronic component according to claim 12 , wherein the primary portion comprises a circular shape.

14. The electronic component according to claim 12 , wherein the auxiliary portion has an about triangular shape.

15. The electronic component according to claim 12 , wherein the auxiliary portion has a tapered shape.

16. The electronic component according to claim 12 , wherein the auxiliary portion has a tear drop shape.

17. The electronic component according to claim 12 , wherein the auxiliary portion has a third portion between the first and second portions, the third portion having a cross sectional area between the cross sectional areas of the first and second portions.