IP Library Granted Patent US 7,005,329
Granted Patent B2
US 7,005,329 · App. 10/889,919 · Granted Feb 28, 2006

Method for manufacturing semiconductor device

Assignee: Hynix Semiconductor Inc.
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Quick Facts
Patent No.
US 7,005,329
App. No.
10/889,919
Granted
Feb 28, 2006
Kind
B2
Abstract

Disclosed is a method for manufacturing a semiconductor device. The method comprises the steps of: providing a first substrate and a second substrate; forming a capacitor and a gate line on a first surface of the first substrate; forming an insulating layer on a resultant structure of the first substrate; bonding the second substrate to the insulating layer of the first substrate; turning a resultant structure over in such a manner that a second surface of the first substrate is an upper surface of the resultant structure; polishing the second surface of the first substrate by a predetermined thickness; forming an isolation layer for defining an active region by performing an isolation process with respect to the second surface of the first substrate for which a polishing process is finished; and forming a bit line on the active region in the first substrate.

Claims (35)

1. A method for manufacturing a semiconductor device, the method comprising the steps of:

i) providing a first substrate and a second substrate;

ii) forming a capacitor on a first surface of the first substrate;

iii) forming an insulating layer on a resultant structure of the first substrate;

iv) bonding the second substrate to the insulating layer of the first substrate;

v) turning over a resultant structure in such a manner that a second surface of the first substrate is an upper surface of the resultant structure;

vi) polishing the second surface of the first substrate by a predetermined thickness;

vii) forming an isolation layer defining an active region by performing an isolation process with respect to the second surface of the first substrate for which a polishing process is carried out; and

viii) forming a bit line on the active region in the first substrate.

2. The method as claimed in claim 1 , wherein the second substrate is any one selected from a group consisting of a silicon wafer, a glass substrate, and a plastic substrate.

3. The method as claimed in claim 1 , wherein the active region is patterned in such a manner that the active region of each column is uniformly aligned in match with each row.

4. The method as claimed in claim 1 , wherein, in step ii), a gate line is formed with the capacitor.

5. The method as claimed in claim 1 , wherein, in step viii), a gate line is formed with the bit line.

6. A method for manufacturing a semiconductor device, the method comprising the steps of:

i) providing a first substrate and a second substrate;

ii) forming a capacitor and a gate line on a first surface of the first substrate;

iii) forming an insulating layer on a resultant structure of the first substrate;

iv) bonding the second substrate to the insulating layer of the first substrate;

v) turning a resultant structure over in such a manner that a second surface of the first substrate is an upper surface of the resultant structure;

vi) polishing the second surface of the first substrate by a predetermined thickness;

vii) forming an isolation layer for defining an active region by performing an isolation process with respect to the second surface of the first substrate for which an polishing process is finished; and

viii) forming a bit line on the active region in the first substrate.

7. The method as claimed in claim 6 , wherein the second substrate is any one selected from a group consisting of a silicon wafer, a glass substrate, and a plastic substrate.

8. The method as claimed in claim 6 , wherein the active region is patterned in such a manner that the active region of each column is uniformly aligned in match with each row.

9. A method for manufacturing a semiconductor device, the method comprising the steps of:

i) providing a first substrate and a second substrate;

ii) forming a capacitor on a first surface of the first substrate;

iii) forming a first insulating layer on the first substrate including the capacitor

iv) bonding the second substrate to the first insulating layer of the first substrate;

v) turning a resultant structure over in such a manner that a second surface of the first substrate is an upper surface of the resultant structure;

vi) polishing the second surface of the first substrate by a predetermined thickness;

vii) forming an isolation layer for defining an active region by performing an isolation process with respect to the first substrate in which a polishing process is finished; and

viii) forming sequentially a bit line and a gate line on the active region in the first substrate.

10. The method as claimed in claim 9 , wherein the second substrate is any one selected from a group consisting of a silicon wafer, a glass substrate, and a plastic substrate.

11. The method as claimed in claim 9 , wherein the active region is patterned in such a manner that the active region of each column is uniformly aligned in match with each row.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2014
From: SK HYNIX INC
To: INTELLECTUAL DISCOVERY CO., LTD.
Reel/Frame 032421/0488 →
CHANGE OF NAME Recorded Mar 9, 2014
From: HYNIX SEMICONDUCTOR, INC.
To: SK HYNIX INC
Reel/Frame 032421/0496 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2004
From: SHIN, YONG CHUL
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 015569/0190 →
Priority Claims (2)
KR 10-2003-0085792 · Nov 28, 2003 · national
KR 10-2003-0095562 · Dec 23, 2003 · national
Continuity (1)
Related Publication 20050118763A1 · Jun 2, 2005