IP Library Granted Patent US 7,018,921
Granted Patent B2
US 7,018,921 · App. 10/724,093 · Granted Mar 28, 2006

Method of forming metal line in semiconductor device

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Quick Facts
Patent No.
US 7,018,921
App. No.
10/724,093
Granted
Mar 28, 2006
Kind
B2
Abstract

The present invention relates to a method of forming a metal line in a semiconductor device, in which an etch-stopping layer is deposited between the interlayer insulation films and then over-etching is performed by using the etch-stopping layer as an etching barrier during the etching process for forming the subsequent trenches. Therefore, it is possible to restrain occurrence of parasitic spacers in the trenches.

Claims (10)

1. A method of forming a metal line in a semiconductor device, comprising:

(a) sequentially forming a first interlayer insulation film, an etch-stopping layer, and a second interlayer insulation film on a semiconductor substrate having a predetermined semiconductor structural layer;

(b) forming a contact hole which partially exposes the semiconductor structural layer by performing an etching process using an etching mask for the contact hole;

(c) forming a metal plug to bury the contact hole;

(d) sequentially forming an anti-diffusion film and a third interlayer insulation film on the semiconductor device including the metal plug;

(e) performing an etching process using an etching mask for a trench to form the trench in such a way that the second interlayer insulation film is over-etched by using the etch-stopping layer as an etching barrier; and

(f) forming a metal line to bury the trench.

2. The method of claim 1 , wherein the etch-stopping layer is composed of SiC, SiN, or SiON.

3. The method of claim 1 , wherein the first interlayer insulation film and the second interlayer insulation film are formed by depositing BPSG, PSG, USG, or FSG, or by a film in which fluorine, hydrogen, boron, or phosphorous is locally diffused into SiO or SiO 2 in a substitutional or interstitial manner.

4. The method of claim 1 , wherein the etching process in the step (b) is performed by using a C x H y F z gas (wherein x is any natural number, y is 0 or any natural number, and z is 0 or any natural number, and wherein both y and z do not become 0 simultaneously) as a main etchant gas and an inert gaseous atom or a molecule of O 2 , N 2 , SF 6 , Ar, or He as an additive gas.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2019
From: MAGNACHIP SEMICONDUCTOR, LTD
To: ATRIA TECHNOLOGIES INC.
Reel/Frame 048058/0864 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY ADDRESS PREVIOUSLY RECORDED AT REEL: 024563 FRAME: 0807. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE BY SECURED PARTY. Recorded Nov 25, 2014
From: US BANK NATIONAL ASSOCIATION
To: MAGNACHIP SEMICONDUCTOR LTD.
Reel/Frame 034469/0001 →