Patent Assignment
Reel/Frame 048058/0864
Assignment of Assignor's Interest
Recorded: 2019-01-18
Pages: 7
Assignor
MAGNACHIP SEMICONDUCTOR, LTD
Executed: 2018-06-21
Assignee
ATRIA TECHNOLOGIES INC.
303 TERRY FOX DRIVE, SUITE 300, OTTAWA, K2K 3J1, CANADA
Covered Properties
(36)
High Voltage Metal Oxide Silicon Field Effect Transistor
Patent:
5,831,320 →
Application:
08/756,433 →
Semiconductor Device Having Triple Well Structure
Patent:
5,939,757 →
Application:
08/876,351 →
Semiconductor Device Having a Soi Structure with Substrate Bias Formed Through the Insulator and in Contact with One of the Active Diffusion Layers
Patent:
5,945,712 →
Application:
08/881,944 →
Method for Manufacturing Minute Silicon Mechanical Device
Patent:
5,981,308 →
Application:
08/887,927 →
Method of Metallization in Semiconductor Devices
Patent:
6,159,846 →
Application:
08/936,398 →
Symmetrical Multi-Layer Metal Logic Array Employing Single Gate Connection Pad Region Transistors
Patent:
6,097,042 →
Application:
09/083,950 →
Lateral Bipolar Mode Field Effect Transistor
Patent:
6,084,254 →
Application:
09/105,397 →
Method of Making High Voltage Metal Oxide Silicon Field Effect Transistor
Patent:
6,033,948 →
Application:
09/178,516 →
Method for Fabricating Semiconductor Device Comprising Capacitor and Resistor
Patent:
6,246,084 →
Application:
09/188,408 →
Lead Frame with Heat Spreader and Semiconductor Package Therewith
Patent:
6,239,487 →
Application:
09/223,191 →
Device Isolation Structure and Device Isolation Method for a Semiconductor Power Integrated Circuit
Patent:
6,171,930 →
Application:
09/233,463 →
Method of Fabricating a Semiconductor Device Having Triple Well Structure
Patent:
6,037,203 →
Application:
09/265,545 →
Method of Manufacturing a Semiconductor Device Having a Soi Structure with Substrate Bias Formed Through the Insulator and in Contact with One of the Active Diffusion Layers
Patent:
6,022,765 →
Application:
09/318,341 →
Method of Manufacturing Sram Having Enhanced Cell Ratio
Patent:
6,281,088 →
Application:
09/324,289 →
High Power Semiconductor Device and Fabrication Method Thereof
Patent:
6,448,611 →
Application:
09/588,546 →
Method for manufacturing lateral bipolar mode effect transistor
Patent:
6,358,786 →
Application:
09/591,965 →
Device isolation structure and device isolation method for semiconductor power integrated circuit
Patent:
6,353,254 →
Application:
09/717,304 →
Semiconductor device and method for fabricating the same
Application:
09/828,153 →
Publication:
US 2001/0011760
Method for Manufacturing a Ferroelectric Memory Device
Patent:
6,410,345 →
Application:
09/975,086 →
Method for Manufacturing a High Power Semiconductor Device Having a Field Plate Extendedly Disposed on a Gate
Simultaneous Formation of Bottom Electrodes and Their Respective Openings of Capacitors in Both a Memory Cell Region and Logic Region
Method of Manufacturing Semiconductor Devices Using Nitrification
Patent:
6,653,192 →
Application:
10/310,866 →
Method of Forming Multi Layer Conductive Line in Semiconductor Device
Patent:
6,656,841 →
Application:
10/315,126 →
Method for Forming Multi-Layer Metal Line of Semiconductor Device
Method of Forming Metal Line in Semiconductor Device
Method for Fabricating Transistor of Semiconductor Device
Semiconductor Device and Method for Fabricating the Same
Method for Fabricating Mems Device Package That Includes Grinding Mems Device Wafer to Expose Array Pads Corresponding to a Cap Wafer
Package of Mems Device and Method for Fabricating the Same
Package of Mems Device and Method for Fabricating the Same
Mems Package That Includes Mems Device Wafer Bonded to Cap Wafer and Exposed Array Pads
Semiconductor Device and Method for Fabricating the Same
Capacitive Humidity Sensor
Photo Sensor Module
Photo Sensor Module
Capacitive Humidity Sensor
Application:
15/419,101 →
Publication:
US 2017/0138882
Related Assignments
(1)
Other recorded transfers of the patents in this record — the chain of ownership.