Semiconductor varactor with reduced parasitic resistance
A semiconductor varactor with reduced parasitic resistance. A contact isolation structure ( 32 ) is formed in a well region ( 20 ). The gate contact structures ( 70 ) are formed above the contact isolation structure ( 32 ) reducing the parasitic resistance. In addition, contact structures are formed on the gate layer ( 50 ) over the well regions ( 20 ) is a further embodiment to reduce the parasitic resistance.
1. A method for forming a low resistance semiconductor varactor, comprising
providing a semiconductor substrate with at least a first isolation region and a second isolation region separated by a first distance;
forming a well region of a first conductivity type in said semiconductor substrate between said first isolation region and said second isolation region;
forming at least a first and second active regions in said well region by forming a contact isolation structure in said well region between said first isolation region and said second isolation region;
forming contact regions of the first conductivity type in said first and second active regions;
forming a gate dielectric layer on said first active region and said second active region;
forming a gate layer on said gate dielectric layer wherein said gate layer overlies said first active region, said second active region, and said contact isolation structure; and
forming electrical contacts to sad gate conductive layer wherein said electrical contacts are formed over said contact isolation structure.
2. The method of claim 1 wherein said first and second isolation regions comprise STI structures.
3. The method of claim 1 wherein said contact isolation structure comprises a STI structure.
4. A method of forming a semiconductor varactor, comprising:
forming a well region of a first conductivity type in a semiconductor substrate;
forming a gate dielectric layer on said well region;
forming a gate layer on said gate dielectric layer;
forming contact regions of the first conductivity type in said well region of a first conductivity type wherein said contact regions are formed using a source and drain region implantation formation process; and
forming gate layer contacts to said gate conductive layer wherein said gate layer contacts overlie an isolation region.
5. The method of claim 4 further comprising forming sidewall structures adjacent to said gate layer.
6. The method of claim 5 wherein said well region is n-type.
7. The method of claim 5 wherein said well region is p-type.