IP Library Granted Patent US 7,053,701
Granted Patent B2
US 7,053,701 · App. 10/702,018 · Granted May 30, 2006

Power amplifier output stage with multiple power states and improved efficiency

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Quick Facts
Patent No.
US 7,053,701
App. No.
10/702,018
Granted
May 30, 2006
Kind
B2
Abstract

A power amplifier output stage that provides multiple power states and mechanisms for enhancing the efficiency of each of its power states. A power amplifier output stage according to the present techniques includes a first output device for driving a load in a first power state and a second output device for driving the load in a second power state along with a matching network for the first power state and a circuit for adapting the matching network to the second power state.

Claims (46)

1. A power amplifier, comprising:

first output device for driving a load in a first power state;

second output device for driving the load in a second power state such that the first output device does not drive the load in the second power state and the second output device does not drive the load in the first power state;

adapting circuit coupled between the first output device and the second output device that adapts a matching network for the first power state to the second power state.

2. The power amplifier of claim 1 , wherein the adapting circuit includes a set of components for transforming an impedance presented to an output node of the first output device to an impedance presented to an output node of the second output device.

3. The power amplifier of claim 2 , wherein the impedance presented to the output node of the second output device is selected to optimize an efficiency of the power amplifier in the second power state.

4. The power amplifier of claim 2 , wherein the impedance presented to the output node of the first output device is selected to optimize an efficiency of the power amplifier in the first power state.

5. The power amplifier of claim 1 , wherein the adapting circuit includes a device for switching between the first and second power states.

6. A power amplifier, comprising:

first output device for driving a load in a first power state;

second output device for driving the load in a second power state;

matching network for the first power state;

circuit for adapting the matching network to the second power state wherein the circuit for adapting includes a device for switching between the first and second power states and a circuit for maintaining an off state of the device for switching when in the second power state.

7. The power amplifier of claim 1 , wherein the first power state is a higher power state and the second power state is a lower power state.

8. A power amplifier, comprising:

first output device for driving a load in a first power state;

second output device for driving the load in a second power state such that the first output device does not drive the load in the second power state and the second output device does not drive the load in the first power state;

circuit for adapting a matching network for the first power state to the second power state wherein the circuit for adapting includes a capacitor and an inductor that are selected to transform an impedance presented to an output node of the first output device to an impedance presented to an output node of the second output device.

9. A power amplifier, comprising:

first output device for driving a load in a first power state;

second output device for driving the load in a second power state;

matching network for the first power state;

circuit for adapting the matching network to the second power state wherein the circuit for adapting includes a capacitor and an inductor that are selected to transform an impedance presented to an output node of the first output device to an impedance presented to an output node of the second output device and further comprising a circuit for preventing the inductor from substantially loading the output node of the first output device in the first power state.

10. A method for providing multiple power states in a power amplifier, comprising:

providing a first output device for driving a load in a first power state;

providing a second output device for driving the load in a second power state such that the first output device does not drive the load in the second power state and the second output device does not drive the load in the first power state;

adapting a matching network for the first power state to the second power state by coupling an adapting circuit between the first output device and the second output device.

11. The method of claim 10 , wherein adapting includes transforming an impedance presented to an output node of the first output device to an impedance presented to an output node of the second output device.

12. The method of claim 11 , further comprising selecting the impedance presented to the output node of the second output device to optimize an efficiency of the power amplifier in the second power state.

13. The method of claim 10 , further comprising selecting the impedance presented to the output node of the first output device to optimize an efficiency of the power amplifier in the first power state.

14. The method of claim 10 , wherein adapting includes switching a device for switching between the first and second power states.

15. A method for providing multiple power states in a power amplifier, comprising:

providing a first output device for driving a load in a first power state;

providing a second output device for driving the load in a second power state;

providing a matching network for the first power state;

adapting the matching network to the second power state wherein adapting includes switching a device for switching between the first and second power states and maintaining an off state of the device for switching when in the second power state.

16. The method of claim 10 , wherein providing a first output device for driving a load in a first power state comprises providing the first output device for driving the load in a higher power state and providing a second output device for driving the load in a second power state comprises providing the second output device for driving the load in a lower power state.

17. A method for providing multiple power states in a power amplifier, comprising:

providing a first output device for driving a load in a first power state;

providing a second output device for driving the load in a second power state such that the first output device does not drive the load in the second power state and the second output device does not drive the load in the first power state;

adapting a matching network for the first power state to the second power state wherein adapting includes selecting a capacitor and an inductor to transform an impedance presented to an output node of the first output device to an impedance presented to an output node of the second output device.

18. A method for providing multiple power states in a power amplifier, comprising:

providing a first output device for driving a load in a first power state;

providing a second output device for driving the load in a second power state;

providing a matching network for the first power state;

adapting the matching network to the second power state wherein adapting includes selecting a capacitor and an inductor to transform an impedance presented to an output node of the first output device to an impedance presented to an output node of the second output device and further comprising preventing the inductor from substantially loading the output node of the first output device in the first power state.

Assignments (13)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
RELEASE OF SECURITY INTEREST Recorded May 15, 2013
From: CITICORP NORTH AMERICA, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 030422/0001 →
MERGER Recorded May 7, 2013
From: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 030369/0703 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2006
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD
To: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.
Reel/Frame 017675/0434 →
SECURITY AGREEMENT Recorded Feb 24, 2006
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: CITICORP NORTH AMERICA, INC.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.
Reel/Frame 017206/0666 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2004
From: VICE, MICHAEL W.
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 014385/0275 →
Continuity (1)
Related Publication 20050093633A1 · May 5, 2005