Semiconductor device placing high, medium, and low voltage transistors on the same substrate

1. A method for forming three kinds of MOS transistors on a single semiconductor substrate, said three kinds of MOS transistors each being provided with gate oxides of differing thicknesses, comprising the steps of:

(a) forming a dielectric layer for device isolation on a surface of the semiconductor substrate for defining first, second, and third regions;

(b) depositing buffer oxide layers on a surface of said semiconductor substrate each overlying said first, second, and third regions;

(c) forming an oxidation resistance layer to have an opening for exposing said first region and to mask said second and third regions;

(d) performing a first thermal oxidation process for forming a first gate oxide layer by increasing a layer thickness of said oxide layer overlaying said first region;

(e) removing said oxidation resistance layer;

(f) depositing a first polysilicon layer over a surface of said semiconductor substrate to be pattered for forming a first gate electrode on said first gate oxide layer;

(g) forming a resist pattern to have an opening for exposing said third region and to mask said first, and said second regions;

(h) removing said buffer oxide layer on said third region using said resist pattern as a mask;

(i) removing said resist pattern;

(j) performing a second thermal oxidation process for forming a second gate oxide layer by increasing a layer thickness of said buffer oxide layer overlaying said second region, having a thickness different from said first gate oxide, and for forming a third gate oxide layer by increasing a layer thickness of said buffer oxide layer overlaying said third region, having a thickness different from said first, and said second gate oxides;

(k) depositing a second polysilicon layer over the surface of said semiconductor substrate; and

(l) patterning said second polysilicon layer for forming second, and third gate electrodes on said second, and third gate oxide layers, respectively.

2. The method according to claim 1 , wherein said oxidation resistance layer essentially consists of silicon nitride.

3. The method according to claim 1 , further comprising the steps of:

forming a first capacitor electrode formed of said first polysilicon layer on said dielectric layer for device isolation, performed during step (f);

forming a capacitor dielectric layer on said first capacitor electrode simultaneously with said second, and said third gate oxide layers, performed during step (i); and

forming a second capacitor electrode formed of said second polysilicon layer on said capacitor dielectric layer, performed during step (k).

4. The method according to claim 3 , wherein said oxidation resistance layer essentially consists of silicon nitride.

5. The method according to claim 1 , further comprising the steps of:

forming a capacitor dielectric layer after forming, and prior to patterning said first polysilicon layer, subsequently a first accumulated pattern of said first gate electrode and said capacitor dielectric layer on said gate oxide layer by patterning said capacitor dielectric layer and said first polysilicon layer, and a second accumulated pattern of said first capacitor electrode formed of said first polysilicon layer and said capacitor dielectric layer on said dielectric layer for device isolation, performed during step (f); and

forming a second capacitor electrode of said second polysilicon layer on said capacitor dielectric layer during step (k).

6. The method according to claim 5 , wherein said oxidation resistance layer essentially consists of silicon nitride.