Memory device with high dielectric constant gate dielectrics and metal floating gates
A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator comprising a metal oxide formed over a substrate. The tunnel insulator and inter-gate insulator have dielectric constants that are greater than silicon dioxide. Each memory cell has a plurality of doped source/drain regions in a substrate. A pair of transistors in a row are separated by an oxide isolation region comprising a low dielectric constant oxide material. A control gate is formed over the inter-gate insulator.
1. A memory transistor comprising:
a substrate having a plurality of source/drain regions, the source/drain regions having a different conductivity type than the remainder of the substrate;
a composite gate insulator layer overlying the substrate;
a metal floating gate overlying the gate insulator, wherein an upper portion of the metal floating gate is oxidized, thereby defining a metal oxide inter-gate insulator layer; and
a control gate formed on top of the inter-gate insulator layer
wherein the composite gate insulator layer is comprised of aluminum oxide-aluminum-aluminum oxide wherein the aluminum oxide layer is the oxidized portion of the floating gate.
2. The transistor of claim 1 wherein the aluminum oxide is grown by low temperature oxidation.
3. The transistor of claim 1 wherein the composite gate insulator layer is comprised of deposited aluminum oxide-aluminum-deposited aluminum oxide.
4. The transistor of claim 1 wherein the composite gate insulator layer is comprised of PbO—Pb—PbO wherein the upper PbO layer is the oxidized upper portion of the Pb layer.
5. The transistor of claim 1 wherein the control gate is comprised of a metal.