Multiple stacked capacitors formed within an opening with thick capacitor dielectric
For forming stacked capacitors, an opening is formed through at least one semiconductor material. A lower electrode material is patterned within the opening to form a plurality of lower electrodes within the opening. The stacked capacitors are formed with the lower electrodes within the opening by depositing a capacitor dielectric and an upper electrode within the opening. With such a relatively large opening, a capacitor dielectric of the stacked capacitors is deposited with a large thickness for improving reliability of the stacked capacitors.
1. A method of forming a plurality of stacked capacitors, comprising:
A. forming an opening through at least one insulating material;
B. patterning a lower electrode material to form a plurality of lower electrodes within the same one opening; and
C. forming the plurality of stacked capacitors with the plurality of lower electrodes within the same one opening.
2. The method of claim 1 , wherein the opening is formed through a capping layer and a molding layer.
3. The method of claim 1 , wherein each of the lower electrodes includes a respective support part disposed over a respective conductive plug, and includes a wall part disposed along a respective portion of at least one wall of the opening.
4. The method of claim 1 , wherein step B includes:
depositing conformally the lower electrode material on at least one wall of the opening; and
patterning the lower electrode material in a photolithography process for forming the lower electrodes.
5. The method of claim 4 , wherein the photolithography process includes an isotropic (non-directional) etch when the lower electrodes are formed on at least one non-inclined sidewall of the opening.
6. The method of claim 4 , wherein the photolithography process includes an anisotropic (directional) etch when the lower electrodes are formed on at least one inclined sidewall of the opening.
7. The method of claim 1 , wherein step A includes:
forming at least one inclined sidewall for the opening.
8. The method of claim 1 , wherein the step C includes the steps of:
depositing a capacitor dielectric on the lower electrodes; and
depositing a upper electrode on the capacitor dielectric.
9. The method of claim 8 , wherein the capacitor dielectric is comprised of one of a high-K dielectric or a ferroelectric material.
10. The method of claim 8 , wherein the upper electrode is continuous over a plurality of openings, with each opening having a respective plurality of stacked capacitors formed therein.
11. The method of claim 8 , wherein the upper electrode is continuous over a column of stacked capacitors formed through a plurality of openings.
12. The method of claim 8 , further comprising:
depositing an upper insulating layer over the upper electrode; and
forming an interconnect plug through the upper insulating layer within the opening and to be coupled to the upper electrode.
13. The method of claim 8 , further comprising:
depositing an upper insulating layer over the upper electrode; and
forming an interconnect plug through the upper insulating layer outside of the opening over a mold layer and to be coupled to the upper electrode.
14. The method of claim 8 , further comprising:
forming the opening through a capping layer and a molding layer; and
planarizing down to the capping layer after step C such that the lower electrodes, the capacitor dielectric, and the upper electrode are contained within the opening.
15. The method of claim 8 , further comprising:
forming the opening through a capping layer and a molding layer; and
forming the lower electrodes, the capacitor dielectric, and the upper electrode over a portion of the capping layer.
16. The method of claim 1 , wherein the opening has a square shape, and wherein each lower electrode is formed at a respective corner of the opening.
17. The method of claim 1 , wherein the opening has a groove shape, and wherein the lower electrodes are formed along sides of the opening.
18. The method of claim 1 , wherein the stacked capacitors are part of a DRAM (dynamic random access memory) device or a ferroelectric memory device.
19. A method of forming a plurality of stacked capacitors, comprising:
A. forming an opening through at least one insulating material;
B. patterning a lower electrode material to form a plurality of lower electrodes within the same one opening;
C. forming the plurality of stacked capacitors with the plurality of lower electrodes within the same one opening; and
D. filling the opening with a buffer insulating layer.
20. The method of claim 19 , wherein each of the lower electrodes includes a respective support part disposed over a respective conductive plug, and includes a wall part disposed along a respective portion of at least one wall of the opening.
21. The method of claim 19 , wherein step B includes:
depositing conformally the lower electrode material on at least one wall of the opening; and
patterning the lower electrode material in a photolithography process for forming the lower electrodes.
22. The method of claim 21 , wherein the photolithography process includes an isotropic (non-directional) etch when the lower electrodes are formed on at least one non-inclined sidewall of the opening.
23. The method of claim 21 , wherein the photolithography process includes an anisotropic (directional) etch when the lower electrodes are formed on at least one inclined sidewall of the opening.
24. The method of claim 19 , wherein the step C includes the steps of:
depositing a capacitor dielectric on the lower electrodes; and
depositing a upper electrode on the capacitor dielectric.
25. The method of claim 24 , wherein the capacitor dielectric is comprised of one of a high-K dielectric or a ferroelectric material.
26. The method of claim 24 , wherein the upper electrode is continuous over a plurality of openings, with each opening having a respective plurality of stacked capacitors formed therein.
27. The method of claim 24 , wherein the upper electrode is continuous over a column of stacked capacitors formed through a plurality of openings.
28. The method of claim 19 , wherein the stacked capacitors are part of a DRAM (dynamic random access memory) device or a ferroelectric memory device.
29. A method of forming a plurality of stacked capacitors, comprising:
A. forming an opening through at least one insulating material;
B. patterning a lower electrode material to form a plurality of lower electrodes within the same one opening;
C. forming the plurality of stacked capacitors with the plurality of lower electrodes within the same one opening; and
D. filling the opening with an upper electrode.
30. The method of claim 29 , wherein each of the lower electrodes includes a respective support part disposed over a respective conductive plug, and includes a wall part disposed along a respective portion of at least one wall of the opening.
31. The method of claim 29 , wherein step B includes:
depositing conformally the lower electrode material on at least one wall of the opening; and
patterning the lower electrode material in a photolithography process for forming the lower electrodes.
32. The method of claim 31 , wherein the photolithography process includes an isotropic (non-directional) etch when the lower electrodes are formed on at least one non-inclined sidewall of the opening.
33. The method of claim 31 , wherein the photolithography process includes an anisotropic (directional) etch when the lower electrodes are formed on at least one inclined sidewall of the opening.
34. The method of claim 29 , wherein the step C includes the steps of:
depositing a capacitor dielectric on the lower electrodes; and
depositing a upper electrode on the capacitor dielectric.
35. The method of claim 34 , wherein the capacitor dielectric is comprised of one of a high-K dielectric or a ferroelectric material.
36. The method of claim 34 , wherein the upper electrode is continuous over a plurality of openings, with each opening having a respective plurality of stacked capacitors formed therein.
37. The method of claim 34 , wherein the upper electrode is continuous over a column of stacked capacitors formed through a plurality of openings.