Method and apparatus for nonvolatile memory
View Patent ↗Method and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for nonvolatile memory device. The device has a strain source, an injection filter, a tunneling gate, a ballistic gate, a charge storage region, a source, and a drain with a channel defined between the source and drain. The strain source permits piezo-effect in ballistic charges transport to enable the piezo-ballistic-charges injection mechanism. The injection filter permits transporting of charge carriers of one polarity type from the tunneling gate through the blocking material and the ballistic gate to the charge storage region while blocking the transport of charge carriers of an opposite polarity from the ballistic gate to the tunneling gate. The present invention further provides an energy band engineering method permitting the memory device be operated without suffering from disturbs, from dielectric breakdown, from impact ionization, and from undesirable RC effects.
1. A nonvolatile memory device, comprising:
a charge storage region;
a ballistic gate disposed adjacent to and insulated from the charge storage region;
a tunneling gate disposed adjacent to and insulated from the ballistic gate; and
a strain source providing a mechanical stress for generating Piezo-effect in at least one of the tunneling and the ballistic gates.
2. The memory device of claim 1 , further comprising:
a charge injection filter disposed in between the ballistic gate and the tunneling gate, wherein the charge injection filter permits transporting of charge carriers of one polarity type from the tunneling gate through the ballistic gate to the charge storage region and blocks transporting of charge carriers of an opposite polarity type from the ballistic gate to the tunneling gate.
3. The memory device of claim 2 , wherein the charge injection filter comprises:
a first dielectric disposed adjacent to the ballistic gate; and
a second dielectric disposed adjacent to the first dielectric, wherein the first dielectric has an energy band gap narrower than an energy band gap of the second dielectric.
4. The memory device of claim 3 , wherein a product of a dielectric constant of the first dielectric and a thickness of the second dielectric is substantially greater than a product of a dielectric constant of the second dielectric and a thickness of the first dielectric.
5. The memory device of claim 1 , further comprising:
means for injecting electrons from the tunneling gate through the ballistic gate onto the charge storage region; and
means for injecting holes from the tunneling gate through the ballistic gate onto the charge storage region.
6. The memory device of claim 5 , wherein the holes comprise light-holes.
7. A nonvolatile memory device, comprising:
a body of a semiconductor material having a first conductivity type;
a first and a second spaced-apart regions formed in the body and having a second conductivity type, with a channel region of the body defined there between;
a charge storage region disposed adjacent to and insulated from the channel region;
a ballistic gate disposed adjacent to and insulated from the charge storage region;
a tunneling gate disposed adjacent to and insulated from the ballistic gate; and
a strain source providing a mechanical stress for generating Piezo-effect in at least one of the tunneling and the ballistic gates.
8. The memory device of claim 7 , further comprising:
a charge injection filter disposed in between the ballistic gate and the tunneling gate, wherein the charge injection filter permits transporting of charge carriers of one polarity type from the tunneling gate through the ballistic gate to the charge storage region and blocks transporting of charge carriers of an opposite polarity type from the ballistic gate to the tunneling gate.
9. The memory device of claim 8 , wherein the charge injection filter comprises:
a first dielectric disposed adjacent to the ballistic gate; and
a second dielectric disposed adjacent to the first dielectric, wherein the first dielectric has an energy band gap narrower than an energy band gap of the second dielectric.
10. The memory device of claim 9 , wherein a product of a dielectric constant of the first dielectric and a thickness of the second dielectric is substantially greater than a product of a dielectric constant of the second dielectric and a thickness of the first dielectric.
11. The memory device of claim 9 , wherein the second dielectric comprises oxide, and the first dielectric comprises material selected from the group consisting of nitride, oxynitride, Al 2 O 3 , HfO 2 , TiO 2 , ZrO 2 , Ta 2 O 5 , and alloys formed thereof.
12. The memory device of claim 9 , wherein the second dielectric comprises oxynitride, and the first dielectric comprises material selected from the group consisting of nitride, Al 2 O 3 , HfO 2 , TiO 2 , ZrO 2 , Ta 2 O 5 , and alloys formed thereof.
13. The memory device of claim 7 , wherein the charge storage region comprises polysilicon.
14. The memory device of claim 7 , wherein the charge storage region comprises a plurality of spaced-apart nano-crystals of a semiconductor material.
15. The memory device of claim 7 , wherein the charge storage region comprises a dielectric having a plurality of charge storing traps.
16. The memory device of claim 7 , further comprising:
means for injecting electrons from the tunneling gate through the ballistic gate onto the charge storage region; and
means for injecting holes from the tunneling gate through the ballistic gate onto the charge storage region.
17. The memory device of claim 16 , wherein the holes comprise light-holes.
18. The memory device of claim 7 , wherein the mechanical stress is a tensile stress.
19. The memory device of claim 7 , wherein the mechanical stress is a compressive stress.
20. The memory device of claim 7 , wherein the strain source is a first strain source and the mechanical stress is a first mechanical stress, and further comprising:
a second strain source providing a second mechanical stress to at least one of the tunneling and the ballistic gates.
21. The memory device of claim 20 , wherein the first mechanical stress comprises a compressive stress and the second mechanical stress comprises a tensile stress.
22. The memory device of claim 20 , wherein the first mechanical stress and the second mechanical stress comprise compressive stress.
23. The memory device of claim 20 , wherein the first mechanical stress and the second mechanical stress comprise tensile stress.
24. The memory device of claim 7 , wherein the ballistic gate comprises material selected from the group consisting of Pt, Au, W, Mo, Ru, Ta, TaN, TiN, n+ polysilicon, p+ polysilicon, n+ poly SiGe and p+ poly SiGe.
25. The memory device of claim 7 , wherein the ballistic gate includes:
a first portion disposed generally over and insulated from the first and the second regions; and
a second portion disposed generally over and insulated from the charge storage region.
26. The memory device of claim 25 , wherein the second portion of the ballistic gate is generally thinner than the first portion.
27. The memory device of claim 7 , wherein the charge storage region is disposed in a trench having a sidewall and a bottom formed in the body.
28. The memory device of claim 27 , wherein:
the sidewall of the trench is generally perpendicular to a surface of the body; and
the bottom of the trench is generally parallel to the surface of the body.
29. The memory device of claim 7 , wherein the strain source comprises material selected from the group consisting of nitride, tungsten-silicide, amorphous silicon, poly SiGe, TaN, and TiN.
30. The memory device of claim 7 , wherein the strain source comprises dislocation loops in at least one of the tunneling and the ballistic gates.
31. The memory device of claim 7 , wherein the mechanical stress is at a level in the range of about 50 MPa to about 1 GPa.