IP Library Granted Patent US 7,129,114
Granted Patent B2
US 7,129,114 · App. 10/797,504 · Granted Oct 31, 2006

Methods relating to singulating semiconductor wafers and wafer scale assemblies

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,129,114
App. No.
10/797,504
Granted
Oct 31, 2006
Kind
B2
Abstract

Methods relating to the singulation of dice from semiconductor wafers. Trenches or channels are formed in the bottom surface of a semiconductor wafer, corresponding in location to the wafer streets. The trenches may be formed by etching or through an initial laser cut. The wafer is then singulated along the streets with a laser preferably having a beam narrower than the trenches. Multiple, laterally spaced lasers may be used in combination during a single pass to perform simultaneous singulating cuts. Additional edge protection for integrated circuitry on the active surface of the semiconductor dice may be provided by forming trenches or channels along the streets in the active surface instead of the bottom surface, disposing protective material along the streets and within the trenches prior to singulation and cutting through the wafer, leaving protective material on the sidewalls of the channels.

Claims (47)

1. A method for singulating at least one semiconductor die from a semiconductor wafer, the method comprising:

providing a semiconductor wafer having a body including an active surface and an opposing, bottom surface;

forming at least one trench in the semiconductor wafer body from the bottom surface thereof in alignment with a plurality of streets on the active surface circumscribing a location of at least one semiconductor die; and

cutting from the active surface of the semiconductor wafer body through the semiconductor wafer body with at least one laser beam along the plurality of streets between the active surface of the semiconductor wafer body and the at least one trench.

2. The method of claim 1 , where forming at least one trench in the semiconductor wafer body comprises etching the at least one trench.

3. The method of claim 2 , wherein etching the at least one trench comprises performing a wet etch or a dry etch.

4. The method of claim 2 , wherein etching the at least one trench comprises performing an anisotropic etch or an isotropic etch.

5. The method of claim 2 , further comprising reducing a thickness of the semiconductor wafer body prior to etching the at least one trench.

6. The method of claim 5 , wherein reducing a thickness of the semiconductor wafer body comprises at least one of backgrinding and performing an etch back of the semiconductor wafer body.

7. The method of claim 2 , wherein etching the at least one trench in the semiconductor wafer body comprises etching the at least one trench to a depth of about 60% to about 90% of a thickness of the semiconductor wafer body.

8. The method of claim 1 , further comprising forming the at least one trench to a width greater than a beam width of the at least one laser beam.

9. The method of claim 1 , wherein forming at least one trench in the semiconductor wafer body comprises cutting the at least one trench with at least another laser beam.

10. The method of claim 9 , further comprising reducing a thickness of the semiconductor wafer body prior to cutting the at least one trench.

11. The method of claim 10 , wherein reducing a thickness of the semiconductor wafer body comprises at least one of backgrinding and performing an etch back of the semiconductor wafer body.

12. The method of claim 9 , wherein cutting the at least one trench in the semiconductor wafer body comprises cutting the at least one trench to a depth of about 60% to about 90% of a thickness of the semiconductor wafer body.

13. The method of claim 9 , further comprising traversing the at least another laser beam to impinge the semiconductor wafer body along a path and substantially concurrently traversing the at least one laser beam to impinge the semiconductor wafer body along the same path subsequent to impingement of the at least another laser beam.

14. The method of claim 9 , wherein cutting the at least one trench in the semiconductor wafer body with at least another laser beam comprises substantially concurrently cutting a plurality of laterally adjacent trenches in the semiconductor wafer body with a plurality of laser beams in a single pass across the semiconductor wafer.

15. The method of claim 14 , wherein cutting a plurality of laterally adjacent trenches in the semiconductor wafer body with a plurality of laser beams comprises cutting a plurality of substantially parallel trenches using a plurality of lasers disposed in a row perpendicular to a direction of relative travel between the plurality of lasers and the semiconductor wafer.

16. The method of claim 15 , further comprising cutting a second plurality of substantially parallel trenches using the plurality of lasers after rotationally reorienting either the semiconductor wafer or the row of lasers perpendicular to the direction of relative travel.

17. The method of claim 1 , wherein cutting through the semiconductor wafer body with at least one laser beam along the plurality of streets between the active surface of the semiconductor wafer body and the at least one trench comprises cutting from the bottom surface of the semiconductor wafer body along the at least one trench.

18. The method of claim 1 , wherein cutting through the semiconductor wafer body with at least one laser beam along the plurality of streets between the active surface of the semiconductor wafer body and the at least one trench comprises cutting a path having a width of less than 80 μm.

19. The method of claim 18 , wherein cutting a path having a width of less than 80 μm comprises cutting a path having a width of about 1 μm.

20. The method of claim 1 , wherein cutting through the semiconductor wafer body with at least one laser beam along the plurality of streets between the active surface of the semiconductor wafer and the at least one trench comprises cutting along at least some of the plurality of streets with a plurality of laser beams in a single pass across the semiconductor wafer.

21. The method of claim 20 , wherein cutting along at least some of the plurality of streets with a plurality of laser beams in a single pass across the semiconductor wafer comprises cutting with a plurality of lasers disposed in a row perpendicular to a direction of relative travel between the plurality of lasers and the semiconductor wafer.

22. The method of claim 21 , further comprising cutting along at least some other of the plurality of streets using the plurality of lasers after rotationally reorienting either the semiconductor wafer or the row of lasers perpendicular to the direction of relative travel.

23. The method of claim 1 , wherein forming the at least one trench comprises forming a plurality of trenches respectively circumscribing locations of a plurality of semiconductor dice.

24. A method for singulating at least one semiconductor die from a semiconductor wafer, the method comprising:

providing a semiconductor wafer having a body including an active surface and an opposing, bottom surface;

cutting at least one trench in the semiconductor wafer body from the bottom surface thereof in alignment with a plurality of streets on the active surface circumscribing a location of at least one semiconductor die with at least one laser beam;

cutting through the semiconductor wafer body with at least another laser beam along the plurality of streets between the active surface of the semiconductor wafer body and the at least one trench; and

traversing the at least one laser beam to impinge the semiconductor wafer body along a path and substantially concurrently traversing the at least another laser beam to impinge the semiconductor wafer body along the same path subsequent to impingement of the at least one laser beam.

25. The method of claim 24 , further comprising reducing a thickness of the semiconductor wafer body prior to cutting the at least one trench.

26. The method of claim 25 , wherein reducing a thickness of the semiconductor wafer body comprises at least one of backgrinding and performing an etch back of the semiconductor wafer body.

27. The method of claim 26 , wherein cutting the at least one trench in the semiconductor wafer body comprises cutting the at least one trench to a depth of about 60% to about 90% of a thickness of the semiconductor wafer body.

28. A method for singulating at least one semiconductor die from a semiconductor wafer, the method comprising:

providing a semiconductor wafer having a body including an active surface and an opposing, bottom surface;

cutting substantially concurrently in a single pass across the semiconductor wafer a plurality of substantially parallel, laterally adjacent trenches in the semiconductor wafer body from the bottom surface thereof in alignment with a plurality of streets on the active surface circumscribing a location of at least one semiconductor die with a plurality of laser beams disposed in a row perpendicular to a direction of relative travel between the plurality of lasers and the semiconductor wafer;

cutting a second plurality of substantially parallel trenches using the plurality of lasers after rotationally reorienting either the semiconductor wafer or the row of lasers perpendicular to the direction of relative travel; and

cutting through the semiconductor wafer body with at least another laser beam along the plurality of streets between the active surface of the semiconductor wafer body and the at least one trench.

29. The method of claim 28 , further comprising reducing a thickness of the semiconductor wafer body prior to cutting the plurality of substantially parallel, laterally adjacent trenches.

30. The method of claim 29 , wherein reducing a thickness of the semiconductor wafer body comprises at least one of backgrinding and performing an etch back of the semiconductor wafer body.

31. The method of claim 30 , wherein cutting the plurality of substantially parallel, laterally adjacent trenches in the semiconductor wafer body comprises cutting at least one trench of the plurality of substantially parallel, laterally adjacent trenches to a depth of about 60% to about 90% of a thickness of the semiconductor wafer body.

32. A method for singulating at least one semiconductor die from a semiconductor wafer, the method comprising:

providing a semiconductor wafer having a body including an active surface and an opposing, bottom surface;

forming at least one trench in the semiconductor wafer body from the bottom surface thereof in alignment with a plurality of streets on the active surface circumscribing a location of at least one semiconductor die; and

cutting through the semiconductor wafer body with at least a plurality of lasers disposed in a row perpendicular to a direction of relative travel between the plurality of lasers and the semiconductor wafer along at least some of the plurality of streets between the active surface of the semiconductor wafer body and the at least one trench in a single pass across the semiconductor wafer; and

cutting along at least some other of the plurality of streets using the plurality of lasers after rotationally reorienting either the semiconductor wafer or the row of lasers perpendicular to the direction of relative travel.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2004
From: AKRAM, SALMAN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 015086/0306 →
Continuity (1)
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