IP Library › Granted Patent US 7,129,874
Granted Patent B2
US 7,129,874 · App. 11/149,899 · Granted Oct 31, 2006

Method and apparatus for operating a pipelined ADC circuit

Assignee: Nordic Semiconductor ASA
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,129,874
App. No.
11/149,899
Granted
Oct 31, 2006
Kind
B2
Abstract

An analog-to-digital converter (ADC) circuit that converts an analog input signal into a digital output circuit includes a noise shaping first stage cascaded with a pipelined second stage. The first stage includes a sample-and-hold circuit and a first order modulator, where the first order modulator includes a noise shaping filter, a FLASH ADC and a feedback DAC. A digital dither generator is used to provide a dither signal to the ADC circuit. The second stage includes a switching circuit and an ADC. A calibration filter connected to the second stage calibrates the ADC circuit. A first reconstruction filter and a second reconstruction filter are used to recombine outputs of the first stage and the second stage of the ADC circuit. The ADC circuit allows high resolution analog-to-digital conversion at a low over-sampling rate and low power dissipation levels.

Claims (43)

1. An analog-to-digital converter system for converting an analog input signal to a digital output signal, the system comprising:

a first stage analog-to-digital converter circuit adapted to convert the analog input signal into a first stage digital output;

a digital signal generator adapted to generate a digital test signal, wherein the digital signal generator is further adapted to change an amplitude of the digital test signal based on at least one of a polarity and an amplitude of the analog input signal;

a combiner coupled to the first stage analog-to-digital converter circuit and adapted to combine the digital test signal with the digital output of the first stage analog-to-digital converter circuit;

a residue signal generator adapted to receive the output of the combiner and to generate a residue signal using the output of the combiner and the analog input signal;

a noise shaping circuit adapted to noise shape the residue signal;

a sampling circuit coupled to the output of the noise shaping circuit and adapted to sample the noise shaped residue signal;

a second stage analog-to-digital converter circuit coupled to the output of the sampling circuit and adapted to generate a second stage digital output based on the sampled residue signal; and

a digital correction circuit coupled to the output of the first stage analog-to-digital converter circuit and to the output of the second stage analog-to-digital converter circuit and adapted to combine the first stage digital output and the second stage digital output using a reconstruction filter.

2. An analog-to-digital converter system of claim 1 , wherein the first stage analog-to-digital converter circuit operates at a first operating frequency and the second stage analog-to-digital converter circuit operates at a second operating frequency, wherein the second operating frequency is a fraction of the first operating frequency.

3. An analog-to-digital converter system of claim 2 , wherein the second operating frequency is equal to a Nyquist frequency of the sampling circuit and the first operating frequency is at least twice the Nyquist frequency of the sampling circuit.

4. An analog-to-digital converter system of claim 1 , wherein the digital signal generator is further adapted to change an amplitude of the digital test signal in a manner so as to prevent the second stage analog-to-digital converter circuit from saturating.

5. An analog-to-digital converter system of claim 1 , wherein the digital correction circuit further includes a decimation filter adapted to cancel the effect of the digital test signal from the combination of the first stage digital output and the second stage digital output.

6. An analog-to-digital converter system of claim 1 , wherein the second stage analog-to-digital converter circuit is one of a pipelined analog-to-digital converter circuit or a cyclic analog-to-digital converter circuit and wherein the first stage analog-to-digital converter circuit is a delta sigma analog-to-digital converter circuit.

7. An analog-to-digital converter system of claim 1 , wherein the first stage analog-to-digital converter circuit further includes:

a multiplier coupled to the output of the noise shaping circuit and adapted to multiply the output of the noise shaping circuit;

a feed-forward path adapted to feed-forward the analog input signal to a summer circuit;

the summer circuit adapted to combine the analog input signal and the output of the multiplier; and

a quantizer adapted to generate a quantized output signal based on the combined output of the summer circuit.

8. An analog-to-digital converter system of claim 7 , wherein the quantizer is further adapted to introduce an offset into the quantized output signal.

9. An analog-to-digital converter system of claim 8 , further comprising an offset correction circuit adapted to correct the offset introduced by the quantizer.

10. An analog-to-digital converter system of claim 1 , wherein the second stage analog-to-digital converter circuit includes a calibration filter adapted to correct gain errors and pole errors in the first stage digital output.

11. A method of converting an analog input signal to a digital output signal, the method comprising:

generating a first stage digital output based on the analog input signal;

generating a digital test signal, wherein the amplitude of the digital test signal changes based on at least one of a polarity and an amplitude of the analog input signal;

combining the first stage digital output with the digital test signal;

generating a residue signal from the combination of the first stage digital output and the digital test signal;

noise-shaping the residue signal;

sampling the noise shaped residue signal at a second operating frequency;

generating a second stage digital output signal based on the sampled residue; and

combining the first stage digital output and the second stage digital output in a manner so as to cancel the effect of the digital test signal.

12. A method of claim 11 , wherein generating the first stage digital output includes generating the first stage digital output using a first stage analog-to-digital converter circuit operating at a first frequency, and wherein the second operating frequency is a fraction of the first operating frequency.

13. A method of claim 11 , wherein the second operating frequency is equal to a Nyquist frequency of a sampling circuit used for sampling the noise shaped residue signal and the first operating frequency is at least twice the Nyquist frequency of a sampling circuit.

14. A method of claim 11 , wherein noise-shaping the residue of the first stage analog-to-digital converter circuit further includes providing a gain to the residue of the first stage analog-to-digital converter circuit.

15. A method of claim 11 , further comprising changing the amplitude of the digital test signal in a manner so as to prevent the second stage analog-to-digital converter circuit from saturating.

16. A method of claim 11 , further comprising:

multiplying the noise shaped residue signal;

combining the analog input signal to the multiplied noise shaped residue signal; and

generating a quantized output signal based on the combination of the analog input signal and the multiplied noise shaped residue signal.

17. A method of claim 16 , further comprising:

introducing an offset into the quantized output signal; and

correcting the offset introduced by the quantizer from the combination of the first stage digital output and the second stage digital output.

18. A method of claim 11 , wherein combining the first stage digital output and the second stage digital output includes combining the first stage digital output and the second stage digital output using one of(1) software; (2) hardware or (3) firmware.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2010
From: SNPS PORTUGAL, LDA; MIPSABG CHIPIDEA, LDA; CHIPIDEA MICROELECTRONICS S.A.
To: SYNOPYS, INC.
Reel/Frame 024252/0056 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2007
From: NORDIC SEMICONDUCTORS ASA
To: CHIPIDEA MICROELECTRONICA S.A
Reel/Frame 019390/0147 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2005
From: BJORNSEN, JOHNNY
To: NORDIC SEMICONDUCTOR ASA
Reel/Frame 016861/0548 →
Continuity (2)
Provisional Application 6057901600 · Jun 10, 2004
Related Publication 20050275577A1 · Dec 15, 2005