IP Library Granted Patent US 7,136,108
Granted Patent B2
US 7,136,108 · App. 10/722,323 · Granted Nov 14, 2006

Segment buffer loading in a deinterlacer

Assignee: Darien K. Wallace
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Quick Facts
Patent No.
US 7,136,108
App. No.
10/722,323
Granted
Nov 14, 2006
Kind
B2
Abstract

A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.

Claims (14)

1. An apparatus, comprising:

a memory storing a field of pixels of video information, the field including a plurality A of lines of pixels, wherein each of said lines includes B pixels;

a segment buffer that stores a plurality C of line segments, wherein each line segment includes D pixels and is a segment of a different line of the field, wherein C is less than A and wherein D is less than B, and wherein the segment buffer has a maximum pixel storing capacity of C times D; and

an interpolator mechanism that receives pixels from the segment buffer and generates therefrom interline gap pixels.

2. The apparatus of claim 1 , wherein a first set of pixels is read out of the memory and is written into the segment buffer-at the same time that the interpolator mechanism receives a second set of pixels from the segement buffer and generates therefrom an interline gap pixel.

3. The apparatus of claim 2 , wherein the interpolator mechanism uses some but not all of the line segments of pixels stored in the segment buffer to interpolate the interline gap pixel, and wherein one of the line segments that is not used in the interpolation of the interline gap pixel is overwritten with the first set of pixels that is transferred from the memory.

4. The apparatus of claim 1 , wherein the segment buffer is written with successive C by D pixel segments of pixels of the field of pixels, and wherein each of the segments overlaps another of the segments such that each such pair of overlapping segments shares a plurality of pixels.

5. The apparatus of claim 1 , wherein each segment comprises a plurality of blocks of pixels, and wherein the interpolator mechanism determines whether each of the blocks exhibits a motion characteristic, and wherein if a block is determined to exhibit the motion characteristic then a first type of interpolation is used to generate interline gap pixels for the block, and wherein if the block is determined not to exhibit the motion characteristic then a second type of interpolation is used to generate the interline gap pixels for the block.

6. The apparatus of claim 5 , wherein the interpolator mechanism comprises a motion history buffer, the motion history buffer comprising a plurality of motion history bits, each motion history bit being indicative of whether a corresponding block of pixels exhibits the motion characteristic.

7. The apparatus of claim 1 , further comprising:

a memory controller that retrieves pixels from the memory that stores the field of pixels, and that writes the pixels retrieved into the segment buffer.

8. The apparatus of claim 1 , wherein the field of pixels is a field of interest, wherein the memory also stores a second field of pixels that precedes the field of interest, wherein the memory also stores a third field of pixels that is subsequent to the field of interest, and wherein the apparatus further comprises:

a second segment buffer through which pixels of the second field are passed to the the interpolator mechanism; and

a third segment buffer through which pixels of the third field are passed to the interpolator mechanism.

Assignments (5)
MERGER Recorded Dec 30, 2015
From: DENACE ENTERPRISE CO., L.L.C.
To: F. POSZAT HU, L.L.C.
Reel/Frame 037387/0300 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2008
From: WALLACE, DARIEN KENNETH
To: DENACE ENTERPRISE CO., L.L.C.
Reel/Frame 021936/0714 →
CORRECTIVE ASSIGNMENT TO CORRECT THE MISTYPED ASSIGNEE NAME IN THE RECORDATION NOTICE PREVIOUSLY RECORDED ON REEL 015507 FRAME 0586. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTION OF THE ASSIGNEE NAME FROM "VLMA MICROSYSTEMS CORPORATION" TO "VIMA MICROSYSTEMS CORPORATION". Recorded Mar 16, 2008
From: NAGAKURA, CLYDE H; ZHOU, QINGGANG; CHAN, THOMAS M
To: VIMA MICROSYSTEMS CORPORATION
Reel/Frame 020654/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2006
From: VIMA MICROSYSTEMS CORPORATION
To: WALLACE, DARIEN K.
Reel/Frame 018325/0914 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2004
From: NAGAKURA, CLYDE H.; ZHOU, QINGGANG; CHAN, THOMAS M.
To: VLMA MICROSYSTEMS CORPORATION
Reel/Frame 015507/0586 →
Continuity (2)
Continuation In Part 1023562800 · Sep 4, 2002
Related Publication 20040160529A1 · Aug 19, 2004