Phase-locked loops
A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control current and varies the control current in proportion to an inverse of N squared. N is the ratio of the output frequency of the PLL system to the reference frequency of the PLL system. The varying of the control current compensates for bandwidth changes of the PLL system.
1. A method for operating a phase-locked loop (PLL), said method comprising:
providing a control current; and
varying the control current in proportion to the inverse of N squared, wherein N is a ratio of an output frequency of the PLL to a reference frequency of the PLL, wherein varying the control current compensates for bandwidth changes of the PLL.
2. The method of claim 1 , wherein varying includes varying a magnitude of the control current.
3. The method of claim 1 , wherein varying includes altering current flow provided by at least one current source, wherein the at least one current source provides the control current.
4. The method of claim 3 , wherein the at least one current source is disposed in a charge pump, the charge pump disposed in the PLL.
5. The method of claim 3 , further including receiving a value of N, wherein the altering is based on the value of N.
6. A method for operating a phase-locked loop (PLL), said method comprising:
providing a detector; and
varying the gain of the detector in proportion to the inverse of N squared, wherein N is a ratio of an output frequency of the PLL to a reference frequency of the PLL, wherein varying the gain of the detector compensates for bandwidth changes of the PLL.
7. The method of claim 6 , wherein the detector includes at least one of a phase detector and a frequency detector.
8. A phase-locked loop (PLL), comprising:
a current generating device configured to generate a control current; and
a switching module configured to vary the control current in proportion to the inverse of N squared, wherein N is a ratio of an output frequency of the PLL to a reference frequency of the PLL.
9. The phase-locked loop of claim 8 , wherein the current generating device includes at least one current source and at least one switch that controls the flow through the at least one current source.
10. The phase-locked loop of claim 9 , wherein the switching module is configured to activate the at least one switch based on a value of N programmed into the PLL.
11. The phase-locked loop of claim 9 , wherein the switching module is configured to activate the at least one switch based on a threshold range of N.
12. The phase-locked loop of claim 8 , wherein the current generating device is a charge pump.
13. The phase-locked loop of claim 12 , further including a loop filter, an oscillator, a divide-by-N module, and a phase/frequency detection device, wherein the loop filter is disposed between the charge pump and the oscillator, the divide-by-N module is disposed between the oscillator and the phase/frequency device, the phase/frequency device is coupled to the charge pump.
14. The phase-locked loop of claim 13 , wherein the charge pump, the loop filter, the oscillator, the divide-by-N module, and the phase/frequency detection device are disposed on a single semiconductor chip.
15. A phase-locked loop (PLL), comprising:
a detector; and
a switching module configured to vary the gain of the detector in proportion to the inverse of N squared, wherein N is a ratio of an output frequency of the PLL to a reference frequency of the PLL.
16. The phase-locked loop of claim 15 , wherein the detector includes one of a phase detector and a frequency detector.
17. The phase-locked loop of claim 16 , further including a loop filter, an oscillator, and a divide-by-N module, the loop filter disposed between the detector and the oscillator, the divide-by-N module disposed between the oscillator and the detector.
18. The phase-locked loop of claim 17 , wherein the loop filter, the oscillator, the divide-by-N module, and the detector are disposed on a single semiconductor chip.