Semiconductor device with isolated storage capacitor and its manufacturing method
A first semiconductor layer that makes a capacitance coupling with a gate electrode of a thin film transistor through a gate insulating layer and a second semiconductor layer that makes a capacitance coupling with a storage capacitor line of a storage capacitor through the gate insulating layer are formed separately. Also, the first semiconductor layer and the second semiconductor layer are connected by a metal wiring. The gate electrode of the thin film transistor makes capacitance coupling with the first semiconductor layer and the storage capacitor line of the storage capacitor makes capacitance coupling with the second semiconductor layer independently. Voltage are induced in the first semiconductor layer and the second semiconductor layer independently. Since there will be no big discrepancy in voltage in the gate insulating layer, the dielectric break down and the leakage can be prevented.
1. A semiconductor device comprising:
a substrate;
a thin film transistor disposed on the substrate;
a storage capacitor disposed adjacent the thin film transistor and keeping a voltage supplied through the thin film transistor;
a first semiconductor portion making a first capacitance coupling with a gate electrode of the thin film transistor;
a second semiconductor portion making a second capacitance coupling with a storage capacitor electrode of the storage capacitor, the second semiconductor portion not being in a physical contact with the first semiconductor portion;
a metal wiring connecting the first semiconductor portion and the second semiconductor portion; and
a pixel electrode connected to the metal wiring,
wherein the second semiconductor portion is disposed between the substrate and the storage capacitor electrode.
2. The semiconductor device of claim 1 , wherein the storage capacitor electrode is disposed parallel to the gate electrode.
3. The semiconductor device of claim 1 , wherein the thin film transistor comprises a p-type channel or an n-type channel.
4. The semiconductor device of claim 1 , wherein the first and second conductor portions are formed from a semiconductor layer disposed on the substrate.
5. The semiconductor device of claim 1 , wherein the first semiconductor portion is bent so that the first semiconductor portion intersects a gate line that comprises the gate electrode.
6. The semiconductor device of claim 5 , wherein the bending of the first semiconductor portion is symmetrical with respect to a center line that is normal to the gate line.
7. A manufacturing method of a semiconductor device, comprising:
providing a substrate;
forming a first semiconductor portion and a second semiconductor portion on the substrate so that the first semiconductor portion is physically separated from the second semiconductor portion;
forming an insulating film on the first semiconductor portion and the second semiconductor portion;
forming a gate electrode on the insulating film so that the gate electrode and the first semiconductor portion are part of a thin film transistor;
forming a storage capacitor electrode on the insulating film so that the storage capacitor electrode and the second semiconductor portion are part of a storage capacitor;
forming a source region and a drain region in the first semiconductor layer;
forming a metal wiring connecting the first semiconductor portion and the second conductor portion;
forming an interlayer insulating film over the first and second semiconductor portions;
forming a first contact hole in the interlayer insulating film so as to provide a contact to the first semiconductor portion;
forming a second contact hole in the interlayer insulating film so as to provide a contact to the second semiconductor portion;
forming a planarization insulating film over the metal wiring;
forming a third contact in the planarization insulating film to provide a contact to the metal wiring; and
forming a pixel electrode connected to the metal wiring through the third contact hole.
8. The manufacturing method of the semiconductor device of claim 7 , wherein the source and drain regions are formed by ion implantation.