IP Library › Granted Patent US 7,160,770
Granted Patent B2
US 7,160,770 · App. 10/269,588 · Granted Jan 9, 2007

Method of manufacturing an electronic component including an inter-line insulating layer and a conductor pattern

Assignee: Murata Manufacturing Co., Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,160,770
App. No.
10/269,588
Granted
Jan 9, 2007
Kind
B2
Abstract

A small size electronic component has a small direct current resistance value of a conductor pattern and minimal dimensional irregularity of a conductor pattern. In order to form such a component, a photosensitive conductive paste applied on a ceramic substrate and is then exposed through a photo mask and developed so as to form a lower conductor pattern layer of a coil conductor pattern. Then an insulating paste is applied on the ceramic substrate so as to cover the lower conductor pattern layer and the insulating paste is removed with a solvent until at least the upper surface of the lower conductor pattern layer is exposed so as to form an inter-line insulating layer. Furthermore, after applying a photosensitive conductive paste as a film, the exposure and development operation is conducted again while using the photo mask so as to form an upper conductor pattern layer on the lower conductor pattern layer.

Claims (24)

1. A method of manufacturing an electronic component comprising the steps of:

applying a positive type photosensitive insulating material on an insulating substrate;

exposing the positive type photosensitive insulating material through a photo mask having a light transmitting component corresponding with a conductor pattern;

eliminating the exposed component of the positive type photosensitive insulating material so as to form an inter-line insulating layer having a pattern groove;

applying a negative type photosensitive conductive material on the inter-line insulating layer;

exposing the negative type photosensitive conductive material through the photo mask; and

eliminating the unexposed component of the negative type photosensitive conductive material so as to form a conductor pattern at the position of the pattern groove.

2. The method according to claim 1 , wherein a ratio of a thickness of the inter-line insulating layer and a width of the pattern groove is equal to or less than about 1.

3. The method according to claim 1 , wherein a ratio of a thickness of the conductor pattern and a width of the conductor pattern is equal to or greater than about 1.

4. The method according to claim 1 , wherein the inter-line insulating layer is formed so as to have via holes therein.

5. The method according to claim 1 , wherein the conductor pattern is a coil conductor pattern.

6. The method according to claim 1 , wherein the conductor pattern has a spiral shape.

7. A method of manufacturing an electronic component comprising the steps of:

applying a negative type photosensitive insulating material on an insulating substrate;

exposing the negative type photosensitive insulating material through a photo mask having a light blocking component corresponding with a conductor pattern;

eliminating the unexposed component of the negative type photosensitive insulating material so as to form an inter-line insulating layer having a pattern groove;

applying a positive type photosensitive conductive material on the inter-line insulating;

exposing the positive type photosensitive conductive material through the photo mask; and

eliminating the exposed component of the positive type photosensitive conductive material so as to form a conductor pattern at the position of the pattern groove.

8. The method according to claim 7 , wherein a ratio of a thickness of the inter-line insulating layer and a width of the pattern groove is equal to or less than about 1.

9. The method according to claim 7 , wherein a ratio of a thickness of the conductor pattern and a width of the conductor pattern is equal to or greater than about 1.

10. The method according to claim 7 , wherein the inter-line insulating layer is formed so as to have via holes therein.

11. The method according to claim 7 , wherein the conductor pattern is a coil conductor pattern.

12. The method according to claim 7 , wherein the conductor pattern has a spiral shape.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2006
From: SASAKI, TOSHIYA; KAWAGUCHI, MASAHIKO; AMAYA, KEISHIRO; UCHIYAMA, KAZUYOSHI; TAMEZAWA, EITA
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 018510/0314 →
Priority Claims (2)
JP 10-203124 · Jul 17, 1998 · national
JP 10-208157 · Jul 23, 1998 · national
Continuity (2)
Division 0935003800 · Jul 8, 1999
Related Publication 20030038372A1 · Feb 27, 2003