Silicon on insulator device and layout method of the same
A silicon on insulator (SOI) semiconductor device includes a wire connected to doped regions formed in an active layer of a SOI substrate. A ratio of the area of the wire to the doped region or a ratio of the area of contact holes formed on the wire to the doped region is limited to a predetermined value. When the ratio exceeds the predetermined value, a dummy doped region is added to prevent the device from being damaged during a plasma process.
1. A layout method of a semiconductor device on a silicon on insulator substrate having a semiconductor substrate and an active layer insulated from the semiconductor substrate by a buried oxide layer, the method comprising:
separating the active layer into a plurality of active regions by a field isolation film having a thickness such that a bottom of the field isolation film reaches an upper surface of the buried oxide film;
placing one or more first doped regions in first one or more of the plurality of active regions;
placing an antenna wire in an antenna wiring layer electrically connected to the one or more first doped regions directly or through at least one first connecting wire in at least one lower wiring layer below the antenna wiring layer; and
when a ratio of a total area of the antenna wire to a total area of the one or more first doped regions exceeds a predetermined value, performing at least one of:
adding a dummy doped region in a second one of the plurality of active regions, the dummy doped region being electrically connected to the one or more first doped regions through at least one second connecting wire in the antenna wiring layer and/or in the at least one lower wiring layer;
adding a junction diode formed in a surface of the semiconductor substrate, the junction diode being electrically connected to the one or more first doped regions through at least one second connecting wire in the antenna wiring layer and/or in the at least one lower wiring layer;
dividing the antenna wire into two parts and electrically connecting the two parts through a third connecting wire in an upper wiring layer above the antenna wiring layer; and
dividing one of the antenna wire and the at least one first connecting wire into two parts, and inserting a buffer between the two parts.
2. The method according to claim 1 , wherein the one or more first doped regions are placed to form at least one source/drain region of a MOS transistor.
3. The method according to claim 1 , wherein said performing adds the dummy doped region.
4. The method according to claim 3 , wherein the dummy doped region functions only to form a capacitance between the dummy doped region and the semiconductor substrate.
5. The method according to claim 1 , wherein the one or more first doped regions are placed to form at least one drain region of a MOS transistor that constitutes an inverter and the at least one drain region constitutes an output terminal of the inverter.
6. The method according to claim 5 , wherein the antenna wire constitutes a signal pass between the inverter and another inverter.
7. The method according to claim 1 , wherein the one or more first doped regions are placed to form at least one drain region of a MOS transistors that constitutes an output terminal of a circuit block.
8. A layout method of a semiconductor device on a silicon on insulator substrate having a semiconductor substrate and an active layer insulated from the semiconductor substrate by a buried oxide layer, the method comprising:
separating the active layer into a plurality of active regions by a field isolation film having a thickness such that a bottom of the field isolation film reaches an upper surface of the buried oxide film;
placing one or more first doped regions in first one or more of the plurality of active regions;
placing an antenna wire in an antenna wiring layer electrically connected to the one or more first doped regions directly or through at least one first connecting wire in at least one lower wiring layer below the antenna wiring layer;
placing at least one connection hole for connecting to the antenna wire; and
when a ratio of a total area of the at least one connection hole to a total area of the one or more first doped regions exceeds a predetermined value, performing at least one of:
adding a dummy doped region in a second one of the plurality of active regions, the dummy doped region being electrically connected to the one or more first doped regions through at least one second connecting wire in the antenna wiring layer and/or in the at least one lower wiring layer;
adding a junction diode formed in a surface of the semiconductor substrate, the junction diode being electrically connected to the one or more first doped regions through at least one second connecting wire in the antenna wiring layer and/or in the at least one lower wiring layer;
dividing the antenna wire into two parts and electrically connecting the two parts through a third connecting wire in an upper wiring layer above the antenna wiring layer; and
dividing one of the antenna wire and the at least one first connecting wire into two parts, and inserting a buffer between the two parts.
9. The method according to claim 8 , the one or more first doped regions are placed to form at least one source/drain region of a MOS transistor.
10. The method according to claim 8 , wherein said performing adds the dummy doped region.
11. The method according to claim 10 , wherein the dummy doped region functions only to form a capacitance between the dummy doped region and the semiconductor substrate.
12. The method according to claim 8 , wherein the one or more first doped regions are placed to form at least one drain region of a MOS transistor that constitutes an inverter and the at least one drain region constitutes an output terminal of the inverter.
13. The method according to claim 12 , wherein the antenna wire constitutes a signal pass between the inverter and another inverter.
14. The method according to claim 8 , wherein the one or more first doped regions are placed to form at least one drain region of a MOS transistor that constitutes an output terminal of a circuit block.