IP Library Granted Patent US 7,197,613
Granted Patent B2
US 7,197,613 · App. 10/721,086 · Granted Mar 27, 2007

Nonvolatile memory

Assignee: Renesas Technology Corp.
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Quick Facts
Patent No.
US 7,197,613
App. No.
10/721,086
Granted
Mar 27, 2007
Kind
B2
Abstract

It is aimed to detect, notify, and save an abnormal area in semiconductor memory for greatly improving reliability. An inside of semiconductor memories provided for a memory card comprises a user area, a substitution area, an area substitution information storage area, and a management area. An inside of semiconductor memories comprises a user area, a substitution area, and a management area. The user area is a data area a user can use. The substitution area is substituted when an error occurs in the user area. The area substitution information storage area stores area substitution area information. The management area stores substitution information. The information processing section performs substitution on two levels as follows. When detecting an operation indicating a symptom of failure in a semiconductor memory area, the information processing section performs area substitution during an idle state of the memory card. When detecting a faulty operation in an area, the information processing section immediately performs area substitution.

Claims (23)

1. A storage device comprising one or more semiconductor memories and an information processing section which performs a first operation for reading data stored in the one or more semiconductor memories and a second operation for writing data to the one or more semiconductor memories in accordance with commands received from outside thereof,

wherein the information processing section detects an error state associated with an area in the semiconductor memory,

substitutes the area during an idle state in which operations are not being performed in response to the commands, when the error state is detected to be a critical state indicating that the area is usable but in a critical condition requiring substitution, and

substitutes the area immediately when the error state is detected to be a limit state indicating that the area is not usable.

2. The storage device according to claim 1 ,

wherein a factor for the information processing section to determine the critical state as the error state comprises one or more of an insufficiency of a substitute free area, a successive retry error, a time over of an erasure time or a program time, an erasure count, an over current of performing a read operation or a write operation, and a low current value of externally supplied power; and

wherein a factor for the information processing section to determine the limit state as the error state comprises one or more of an insufficiency of a substitute free area, a successive retry error, an ECC uncorrectable error at retention failure, a device code unreadable error, a time over of an erasure time or a program time, an erasure count, an over current of performing a read operation or a write operation, and a low current value of externally supplied power.

3. The storage device according to claim 2 , and which is capable of independently setting the factors for the information processing section to determine the critical state and setting the factors for the information processing section to determine the limit state.

4. The storage device according to claim 3 ,

wherein a substitution destination area substituted by the information processing section is a free area in the semiconductor memory or semiconductor memory for substitution only.

5. The storage device according to claim 4 ,

wherein, when the substitution destination area is a free area in the semiconductor memory, the substitution destination area is a physical area controlled by an individual peripheral circuit which controls any of a plurality of sectors provided for a memory mat.

6. The storage device according to claim 5 , wherein a decode method of the device substitutes only data in a substitution origin area for data in the substitution destination area, and after substitution, allows access to the substitution destination area instead of the substituted area, and allows access to an unsubstituted area in the same manner as before the substitution.

7. The storage device according to claim 1 ,

wherein the information processing section notifies an outside of an emergency condition when the error state is indicated to be the limit state.

8. The storage device according to claim 7 , wherein one or more restricting operations, including inhibiting a write operation, are performed in the limit state.

9. The storage device according to claim 8 ,

wherein the information processing section copies data from the substitution origin area to the substitution destination area during the area substitution and corrects a correctable error if it is contained in the data.

10. The storage device according to claim 9 , further comprising:

a detection circuit for detecting an area state;

a notification circuit for notifying the outside of a detection result and an area substitution state;

an area substitution circuit for performing area substitution; and

an area decode management circuit for managing permission or inhibition of access to areas.

Assignments (4)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
MERGER Recorded Aug 13, 2010
From: RENESAS TECHNOLOGY CORP.
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024879/0190 →
CHANGE OF NAME Recorded Aug 13, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024864/0635 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2003
From: SHIBUYA, HIROFUMI; HARA, FUMIO; GOTO, HIROYUKI; SHIOTA, SHIGEMASA
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 014748/0489 →
Priority Claims (1)
JP 2003-018296 · Jan 28, 2003 · national
Continuity (1)
Related Publication 20040158775A1 · Aug 12, 2004