Accelerated scan circuitry and method for reducing scan test data volume and execution time
An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).
1. A scan flip-flop, comprising:
a Scan_In port;
a Data_In port;
a Scan_Enable port;
a CLK port;
a Data_Out port; and
having a means to:
capture data from said Data_In port in one state of a signal on said Scan_Enable port by applying a change to a signal on said CLK port thereby changing said signal on said CLK port to a pre-defined CLK state;
capture data from said Scan_In port in a different state of the signal on said Scan_Enable port by applying said change to said signal on said CLK port, thereby changing it to said pre-defined CLK state;
disable loading data from either of said Scan_In port and said Data_In port in a state other than said pre-defined CLK state of said signal on said CLK port; and
enable reflecting captured data at said Data_Out port by applying said state other than said pre-defined CLK state on said CLK port combined with applying said one state of a signal on said Scan_Enable port, reflected data on said Data_Out port being held constant at other times.
2. A multiplicity of scan flip-flops according to claim 1 , said scan flip-flops incorporated into a circuit structure comprising:
a multiplicity of scan-chains, wherein at least one of said scan-chains comprises a multiplicity of said scan flip-flops, at least one said Scan_Enable port of at least one said scan flip-flop being coupled to a control signal wherein:
in one state, said control signal provides information to select operation of said flip-flop responsive to said Scan_In port or responsive to said Data_In port; and
in another state, said control signal provides information to select operation of said flip-flop to reflect said captured data at its Data_Out port.
3. A boundary scan flip-flop comprising:
a data-in port;
a data-out port;
a scan-in port;
a scan-out port;
a probe-in port;
a probe-out port;
a test port; and
a flip-flop structure;
wherein said flip-flop structure and at least a subset of said ports are adapted to implement at least;
a system operation mode, enabled by one state of said test port, wherein said boundary scan flip-flop propagates a data value of a signal from said data-in port to said data-out port, wherein the propagation of the data value of a signal from said data-in port to said data-out port includes choosing to propagate the data value of a signal from said data-in port, as opposed to a data value of a signal from said probe-in port, based on a state of said flip-flop structure; and
a test operation mode, enabled by a different state of said test port, wherein said boundary scan flip-flop propagates a data value of a signal from said probe-in port to said probe-out port, and captures a data value of a signal on said data-in port for shifting out through said scan-in and scan-out ports.
4. The boundary scan flip-flop as in claim 3 , further comprising:
a first multiplexer adapted to be coupled to said data-in port and to said flip-flop, an output of said first multiplexer adapted to be coupled to said data-out port, the first multiplexer adapted to be responsive to a signal from said test port; and
a second multiplexer adapted to be coupled to said probe-in port and to said data-in port, an output of the second multiplexer adapted to be coupled to said probe-out port, the second multiplexer adapted to be responsive to said signal from said test port.
5. The boundary scan flip-flop as in claim 4 , further comprising:
a logic gate coupled to said flip-flop and to said test port, an output of said logic gate adapted to provide a select input to said second multiplexer.
6. A multiplicity of boundary scan flip-flops as in claim 3 , connected to form a multiplicity of boundary scan chains, wherein at least one of said boundary scan-chains contains a multiplicity of scan segments such that any data in port of any boundary scan flip-flop may be probed during system operation.
7. A multiplicity of boundary scan flip-flops as in claim 6 , wherein at least one compressed test pattern is used during said test operation mode.