Termination arrangement for high speed data rate multi-drop data bit connections

1. A circuit for terminating devices attached to a signal line and driving a receiver or driver, the circuit comprising:

(a) a resistor R 1 in series with the signal line;

(b) a circuit CR 1 comprising a resistor r 2 in series with a switch s 1 , wherein CR 1 is in parallel with R 1 ;

(c) a circuit CR 2 comprising a resistor R 3 in series with switch S 2 , connected at one end to Vcc and at the other end to the receiver or driver;

(d) a circuit CR 3 comprising a resistor R 5 in series with switch S 4 , connected at one end to Vcc and at the other end to the receiver or driver;

(e) a circuit CR 4 comprising a resistor R 6 in series with switch S 5 , connected at one end to GND and at the other end to the receiver or driver;

(f) a circuit CR 5 comprising a resistor R 4 in series with switch S 3 , connected at one end to ground and at the other end to the receiver or driver; and

(g) a capacitor connected between the receiver or transmitter and ground.

2. The circuit of claim 1 , configured in Write mode, wherein:

(a) switch S 1 is ON;

(b) switch S 2 is ON;

(c) switch S 3 is ON;

(d) switch S 4 is ON; and

(e) switch S 5 is ON.

3. The circuit of claim 1 , configured in Read mode, wherein:

(a) switch S 1 is ON;

(b) switch S 1 is OFF;

(c) switch S 1 is OFF;

(d) switch S 1 is OFF; and

(e) switch S 1 is OFF.

4. The circuit of claim 1 , configured in Inactive mode, wherein:

(a) switch S 1 is OFF;

(b) switch S 1 is ON;

(c) switch S 1 is ON;

(d) switch S 1 is OFF; and

(e) switch S 1 is OFF.