Method of fabricating recess transistor in integrated circuit device and recess transistor in integrated circuit device fabricated by the same
Provided is a method of fabricating a recess transistor in an integrated circuit device. In the provided method, a device isolation region, which contacts to the sidewall of a gate trench and a substrate region remaining between the sidewall of the device isolation region and the sidewall of the gate trench, is etched to expose the remaining substrate region. Thereafter, the exposed portion of the remaining substrate region is removed to form a substantially flat bottom of the gate trench. The recess transistor manufactured by the provided method has the same channel length regardless of the locations of the recess transistor in an active region.
1. A method of fabricating a recess transistor, the method comprising:
forming a trench device isolation region on an integrated circuit substrate to define an active region;
forming a gate trench in the active region;
etching the trench device isolation region, which contacts the sidewall of the gate trench, and a substrate region remaining between the sidewall of the trench device isolation region and the sidewall of the gate trench, to expose the remaining substrate region;
removing the exposed portion of the remaining substrate region to form a substantially flat bottom of the gate trench; and
forming a recess gate that fills the gate trench.
2. The method of claim 1 , wherein a portion of the substrate region, which remains between the sidewall of the trench device isolation region and the sidewall of the gate trench, is etched before exposing the remaining substrate region.
3. The method of claim 1 , wherein removing the exposed portion of the remaining substrate region comprises performing isotropic dry etching.
4. The method of claim 1 , wherein removing the exposed portion of the remaining substrate region comprises performing wet etching.
5. The method of claim 1 , wherein forming the gate trench comprises performing anisotropic dry etching.
6. The method of claim 1 , wherein forming the trench device isolation region comprises:
forming a trench on the substrate;
forming an oxide layer on a sidewall of the trench;
filling an insulating layer in the trench; and
planarizing the insulating layer.
7. The method of claim 1 , wherein forming the trench device isolation region comprises:
forming a trench on the substrate;
forming an oxide layer on a sidewall of the trench;
forming a nitride layer conformally on the oxide layer, the nitride layer operating as an etch stopper when exposing the remaining substrate region;
filling the trench with an insulating layer; and
planarizing the insulating layer.
8. The method of claim 1 , further comprising:
before forming the gate trench, forming a source/drain region in the active region; and
forming the gate trench to a depth that is larger than a depth of the source/drain region.
9. A method of fabricating a recess transistor, the method comprising:
forming an isolation region on a substrate to define an active region;
forming a gate trench in the active region;
etching the sidewalls of the isolation region, thereby exposing a protruding substrate region;
etching the protruding substrate region, thereby forming a substantially flat bottom of the gate trench; and
forming a recess gate that fills the gate trench.
10. The method of claim 9 , wherein forming the gate trench comprises:
etching the active region to form a trench; and
etching the sidewalls of the trench.
11. The method of claim 9 , wherein etching the protruding substrate region comprises performing isotropic dry etching.
12. The method of claim 9 , wherein etching the protruding substrate region comprises performing wet etching.
13. The method of claim 9 , wherein forming the gate trench comprises performing anisotropic dry etching.
14. The method of claim 9 , wherein forming the isolation region comprises:
forming a trench on the substrate;
forming an oxide layer on a sidewall of the trench;
filling an insulating layer in the trench; and
planarizing the insulating layer.
15. The method of claim 14 , further comprising forming a nitride layer conformally on the oxide layer, the nitride layer operating as an etch stopper when exposing the protruding substrate region.
16. The method of claim 9 , further comprising:
before forming the gate trench, forming a source/drain region in the active region; and
forming the gate trench to a depth that is larger than a depth of the source/drain region.