IP Library › Granted Patent US 7,221,107
Granted Patent B2
US 7,221,107 · App. 11/105,155 · Granted May 22, 2007

Low frequency electronic ballast for gas discharge lamps

Assignee: Ballastronic, Inc.
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Quick Facts
Patent No.
US 7,221,107
App. No.
11/105,155
Granted
May 22, 2007
Kind
B2
Abstract

An electronic ballast for high intensity gas discharge lamps where the wave form of the lamp current is square wave providing acoustic resonance and flickering free operation. The circuit, having high efficiency, operates in a wide temperature range providing ideal ballast curve and reliable ignition for the lamps. Furthermore, significant energy saving can be achieved by its externally controlled built in dimming capability.

Claims (30)

1. A low frequency square wave electronic ballast for high intensity discharge lamps, comprising:

an input filter connected to a sinusoidal line voltage source as an external power supply,

a bridge rectifier connected to the input filter,

a filtered voltage divider connected to the output of the bridge rectifier providing a DC voltage signal proportional to the average of the rectified sinusoidal line voltage,

an isolated dimming control unit including a low power external switch and an optocoupler providing isolated two-state control signal,

a power factor preregulator connected to the output of said bridge rectifier including a control unit and a boost converter providing sinusoidal input current in phase with the line voltage, and further providing regulated DC output voltage,

a constant power DC current source including a buck converter integrated with a nonlinear function generator, a voltage comparator, and a dimming circuit implementing the ideal full power or dimmed ballast curves for high intensity discharge lamps in their typical lamp voltage range,

an output unit including a full-bridge inverter providing low frequency square wave current avoiding cataphoretic phenomenon of high intensity discharge lamps, a dual frequency driver unit of the full-bridge inverter, a high frequency to low frequency transition unit, a short circuit protection unit, and further including a high frequency ignition circuit providing appropriate ignition signal for high intensity discharge lamps,

a logic supply voltage unit connected to the output of said bridge rectifier providing a first isolated and stabilized logic supply for the isolated dimming control unit, a second isolated and stabilized logic supply for the power factor preregulator, a third isolated and stabilized logic supply for the constant power DC current source, and a fourth isolated and stabilized logic supply for the output unit; wherein

the output of the said power factor preregulator is connected to the input of the said constant power current source, and the output of the said constant power current source is connected to the input of the said output unit, and the output of the said output unit is connected to a high intensity discharge lamp implementing a low frequency square wave electronic ballast providing an acoustic resonance free operation of the lamp; and further wherein

the output of the said filtered voltage divider is connected to the control unit of said power factor preregulator, and the control unit of said power factor preregulator is connected to the control unit of said constant power DC current source providing automatic dimming of the high intensity discharge lamp if the line voltage is out of its predetermined range; and still further wherein

the optocoupler of the said isolated dimming control unit is connected to the control unit of said power factor preregulator and the dimming circuit of the constant power DC current source providing an isoiated external dimming control of the high intensity discharge lamp.

2. The boost converter in accordance with claim 1 , comprising an inductor, a controlled electronic switch, an output capacitor, and a first rectifier implementing the standard boost converter configuration operating in continuous-discontinuous border mode, and further comprising a second rectifier; wherein

the anode of second rectifier is connected to the lower potential end of controlled electronic switch, the cathode of second rectifier is connected to the lower potential end of output capacitor, and the cathode of second rectifier is connected to the said control unit of power factor preregulator providing a stable and noise free signal for the said control unit of power factor preregulator when the current of the inductor decreases to zero value.

3. The control unit of power factor preregulator in accordance with claim 1 , comprising a first resistor, a capacitor, an analog controller, a voltage comparator, and a first low power MOSFET implementing the standard constant ON-time control of said boost converter, and further comprising a window comparator, a second resistor, and a second low power MOSFIT; wherein

the input of the window comparator is connected to the output of said filtered voltage divider, the output of the window comparator and the output of the said optocoupler is connected to the gate of the second low power MOSFET, the second resistor is connected to the drain of the second low power MOSFET, the source of the second low power MOSFET is connected to said first stabilized logic supply and to the common point of the first resistor and capacitor providing transient free transition of the power factor preregulator between the full power and dimmed operation.

4. The buck converter integrated with a nonlinear function generator in accordance with claim 1 , comprising an inductor, a controlled electronic switch, an output capacitor, and a first rectifier implementing the standard buck converter configuration operating in continuous-dis-continuous border mode, and further comprising a second rectifier and a second capacitor; wherein

the anode of die second rectifier is connected to the output capacitor, the cathode of the second rectifier is connected to an end of second capacitor, and the other end of the second capacitor is connected to the cathode of the first rectifier, therefore bootstrapping the output voltage of the buck converter to the potential level of the common point of the controlled electronic switch, the first rectifier and the zero level of said third stabilized logic supply voltage source, and still further comprising a third rectifier, a first resistor, a second resistor, a third resistor, and a fourth resistor; wherein

the first end of the first resistor is connected to the first end of the second and the third resistor, the second end of the second resistor is connected to the anode of the third rectifier, the cathode of the third rectifier is connected to said third stabilized logic supply voltage source, the second end of the third resistor is connected to the first end of the fourth resistor, the second end of the fourth resistor is connected to the zero level of said third stabilized logic supply voltage source, and the common point of the third and the fourth resistor is connected to the inverting input of said voltage comparator providing a nonlinear conversion of the output voltage of the buck converter equal to the voltage of said high intensity discharge lamp in such a way that the lamp power remains the same in their typical lamp voltage range.

5. The dimming circuit in accordance with claim 1 , comprising a low power MOSFET and a capacitor; wherein

the source of the low power MOSFET is connected to the first end of the capacitor, the drain of the low power MOSFET is connected to said third stabilized logic supply voltage source, the gate of the low power MOSFET is controlled by said optocoupler of the isolated dimming control unit, and the second end of the capacitor is connected to the non-inverting input of said voltage comparator providing dimming control of the said constant power DC current source, therefore the dimming of said high intensity discharge lamp.

6. The full-bridge inverter in accordance with claim 1 , comprising a first power MOSFET connected to first MOSFET driver, a second power MOSFET connected to second MOSFIT driver, a third power MOSFET connected to a third MOSFET driver, a fourth power MOSFET connected to a fourth MOSFET driver implementing the standard full-bridge inverter; wherein

the first and the second power MOSFET's are lower electronically controlled switches, the third and the fourth power MOSFET's are the upper electronically controlled switches of the full-bridge inverter, and further comprising a first rectifier, a second rectifier, a first capacitor connected to said fourth MOSFET driver, and a second capacitor connected to said third MOSFET driver; wherein

the cathode of the first rectifier is connected to the first capacitor, the cathode of the second rectifier is connected to the second capacitor, and the anodes of the first and the second rectifiers is connected to said fourth stabilized voltage source, and the zero potential level of the said fourth stabilized voltage source is connected to the common point of the sources of the first and the second power MOSFET's providing logic supply voltage source for the third and the fourth MOSFET drivers during the high and the low frequency operation of the full-bridge inverter, therefore eliminating two extra isolated stabilized logic supplies for said output unit.

7. The high frequency to low frequency transition unit in accordance with claim 1 , comprising a shunt resistor, a reference voltage source, a voltage comparator, a monostable multivibrator; wherein

the shunt resistor is connected in series with the full-bridge inverter, the common point of the shunt resistor and the full-bridge inverter is connected to the inverting input of the voltage comparator, the non-inverting input of the voltage comparator is connected to the reference voltage source, the output of the voltage comparator is connected to the input of the monostable multivibrator, and the output of the said voltage comparator is connected to said dual frequency driver unit of the full-bridge inverter providing a series of inhibition signals for the full-bridge inverter during the transition process from high frequency to low frequency operation of the full-bridge inverter when the load current across the shunt resistor achieves a predetermined value proportional to the reference voltage.

8. The short circuit protection unit in accordance with claim 1 , comprising a voltage comparator, a rectifier, a capacitor, a first resistor, a second resistor, a third resistor, and a fourth resistor; wherein

the first and the second resistor implement a voltage divider connected to said fourth stabilized logic supply voltage source, the common point of the first and the second resistors is connected to the inverting input of the voltage comparator, the third and the fourth resistor and the capacitor are connected in series and their two ends are connected to forth said stabilized logic supply voltage source, the common point of the fourth resistor and the capacitor is connected to the non-inverting input of voltage comparator, the common point of the third and the fourth resistors is connected to the anode of the rectifier, the cathode of the rectifier is connected to the input of said output unit, and the output of the voltage comparator inhibits the said constant power DC current source providing zero current short circuit protection for said output unit.

9. The high frequency ignition circuit in accordance with claim 1 , comprising a transformer having a primary and a secondary winding, and further comprising a capacitor; wherein

the primary winding of the transformer is connected in series with the capacitor, and further connected to the output of said full-bridge inverter, the secondary winding of the transformer is connected in series with said high intensity discharge lamp providing high frequency and an appropriate high voltage sinusoidal ignition signal for said high intensity discharge lamp during the high frequency operation of the said full-bridge inverter.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2005
From: MELIS, JONAS
To: BALLASTRONIC, INC.
Reel/Frame 016471/0776 →
Continuity (1)
Related Publication 20060232220A1 · Oct 19, 2006