IP Library › Granted Patent US 7,221,718
Granted Patent B2
US 7,221,718 · App. 10/354,078 · Granted May 22, 2007

I/Q demodulator and I/Q signal sampling method thereof

Assignee: Samsung Electronics Co., Ltd.
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Quick Facts
Patent No.
US 7,221,718
App. No.
10/354,078
Granted
May 22, 2007
Kind
B2
Abstract

An I/Q demodulator optimized with a minimum amount of hardware. First and second multiplexers generate I and Q signals with respect to an input data signal; and first and second 2-decimation units decimate the I and Q signals generated by the first and second multiplexers, to output effective I and Q signals. A filtering unit filters the effective I and Q signals. As a result, a size of the hardware is reduced, and an operation frequency of the filter is reduced.

Claims (69)

1. An In-phase/Quadrature-phase (I/Q) demodulator, comprising:

a delay unit which delays an input data signal and outputs a delayed input signal;

first and second decimation units which decimate the input data signal and the delayed input signal, respectively;

a first multiplexer which multiplexes the decimated delayed input data signal and a negative of the delayed input signal to output an I signal;

a second multiplexer which multiplexes the decimated non-delayed input data signal and a negative of the non-delayed input signal to output a Q signal; and

first and second filters which filter the I and Q signals, to output effective I and Q signals, respectively.

2. The I/O demodulator of claim 1 , wherein the first and second decimation units perform a 2-decimation.

3. The I/O demodulator of claim 1 , further comprising:

first and second L-upsampling units which L-upsample the I and Q signals output from the first and second multiplexers to provide the upsampled I and Q signals to the first and second filters; and

first and second M-downsampling units which M-downsample the filtered I and Q signals.

4. The I/Q demodulator of claim 3 , wherein the L of each L-upsampling unit is odd.

5. The I/Q demodulator of claim 3 , wherein the L of each L-upsampling unit is even.

6. The I/Q demodulator of claim 1 , wherein:

the first multiplexer sequentially outputs the input data signal, a zero, a negative of the input data signal and a zero; and

the second multiplexer sequentially outputs a zero, the input data signal, a zero and a negative of the input data signal.

7. An In-phase/Quadrature-phase (I/Q) demodulator, comprising:

a delay unit which delays an input data signal and outputs a delayed input signal;

first and second decimation units which decimate the input data signal and the delayed input signal, respectively;

a first multiplexer which multiplexes the decimated delayed input data signal and a negative of the delayed input signal to output an I signal;

a second multiplexer which multiplexes the decimated non-delayed input data signal and a negative of the non-delayed input signal to output a Q signal;

first and second upsampling units which upsample the I and Q signals, respectively;

first and second filters which filter the upsampled I and Q signals, respectively; and

first and second M-downsampling units which downsample the filtered I and Q signals, respectively, to output effective I and Q signals, respectively.

8. The I/O demodulator of claim 7 , wherein the M of each M-downsampling unit is even.

9. The I/Q demodulator of claim 7 , wherein the M of each M-upsampling unit is odd.

10. An In-phase/Quadrature-phase (I/Q) demodulator, comprising:

a first multiplexer which multiplexes an input signal and other signals to output an I signal;

a second multiplexer which multiplexes the input signal and the other signals to output a Q signal;

first and second upsampling units which upsample the I and Q signals, respectively;

first and second delay units which delay the upsampled I and Q signals, respectively;

first and second decimation units which decimate the delayed I and Q signals, respectively;

first and second low pass filters which filter the decimated I and Q signals; and

first and second M-downsampling units which M-downsample the low pass filtered I and Q signals, to output effective I and Q signals, wherein the M of each M-downsampling unit is even.

11. The I/O demodulator of claim 10 , wherein:

the first multiplexer sequentially outputs the input data signal, a zero, a negative of the input data signal and a zero; and

the second multiplexer sequentially outputs a zero, the input data signal, a zero and a negative of the input data signal.

12. An In-phase/Quadrature-phase (I/Q) demodulator, comprising:

a first multiplexer which multiplexes an input signal and other signals to output an I signal;

a second multiplexer which multiplexes the input signal and the other signals to output a Q signal;

first and second upsampling units which upsample the I and Q signals, respectively;

a delay unit which delays the upsampled I signal;

first and second decimation units which decimate the delayed I signal and the Q signal, respectively;

first and second low pass filters which filter the decimated delayed I signal and the decimated Q signal, respectively; and

first and second M-downsampling units which M-downsample the filtered decimated delayed I signal and the filtered decimated Q signal, to output effective I and Q signals, respectively, wherein the M of each M-downsampling unit is odd.

13. The I/Q demodulator of claim 12 , wherein:

the first multiplexer sequentially outputs the input data signal, a zero, a negative of the input data signal and a zero; and

the second multiplexer sequentially outputs a zero, the input data signal, a zero and a negative of the input data signal.

14. An In-phase/Quadrature-phase (I/Q) signal generating method, comprising:

delaying an input data signal and outputting a delayed input signal;

decimating the input data signal and the delayed input signal, respectively;

multiplexing the decimated delayed input data signal and a negative of the delayed input signal to output an I signal;

multiplexing the decimated non-delayed input signal and a negative of the non-delayed input signal to output a Q signal; and

filtering the I and Q signals, to output effective I and Q signals, respectively.

15. The I/Q signal generating method of claim 14 , further comprising:

L-upsampling the I and Q signals output; and

M-downsampling the filtered I and Q signals.

16. The I/Q signal generating method of claim 15 , wherein the L of the L-upsampling is odd.

17. The l/Q signal generating method of claim 15 , wherein the L of the L-upsampling is even.

18. The I/O signal generating method of claim 14 , wherein the decimating performs a 2-decimation.

19. The I/Q signal generating method of claim 14 , wherein:

the I signal is sequentially output as the input data signal, a zero, a negative of the input data signal and a zero; and

the Q signal is sequentially output as a zero, the input data signal, a zero and a negative of the input data signal.

20. An In-phase/Quadrature-phase (I/Q) signal generating method, comprising:

delaying an input data signal and outputting a delayed input data signal;

decimating the input data signal and the delayed input signal, respectively;

multiplexing the decimated delayed input data signal and a negative of the delayed input signal to output an I signal and a Q signal;

upsampling the I and Q signals, respectively;

filtering the upsampled I and Q signals, respectively; and

downsampling the filtered I and Q signals, respectively, to output effective I and Q signals, respectively.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2003
From: PARK, CHAN-SUB
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 013722/0991 →
Priority Claims (1)
KR 2002-11362 · Mar 4, 2002 · national
Continuity (1)
Related Publication 20030165202A1 · Sep 4, 2003