IP Library Granted Patent US 7,226,819
Granted Patent B2
US 7,226,819 · App. 10/970,299 · Granted Jun 5, 2007

Methods for forming wiring and manufacturing thin film transistor and droplet discharging method

Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 7,226,819
App. No.
10/970,299
Granted
Jun 5, 2007
Kind
B2
Abstract

It is required that a line width of a wiring is prevented from being wider to be miniaturized when the wiring or the like is formed by a dropping method typified by an ink-jetting method. The invention provides a method for narrowing (miniaturizing) a line width according to a method different from a conventional method. One feature of the invention is that a plasma treatment is performed before forming a wiring or the like by a dropping method typified by an ink-jetting method. As the result of the plasma treatment, a surface for forming a conductive film is modified to be liquid-repellent. Consequently, a wiring or the like formed by a dropping method can be miniaturized.

Claims (64)

1. A method for manufacturing a thin film transistor comprising: performing a plasma treatment on a surface for forming a gate electrode to form a first liquid-repellent region;

dropping a composition including a material of the gate electrode to form the gate electrode on the first liquid-repellent region of the surface for forming the gate electrode;

performing a plasma treatment on a surface for forming source and drain electrodes to be a second liquid-repellent; and

dropping a composition including a material of the source and drain electrodes to form the source and drain electrodes on the second liquid-repellent region of the surface for forming the source and drain electrodes.

2. A method for manufacturing a thin film transistor comprising:

performing a plasma treatment on a substrate to form a first liquid-repellent region;

dropping a composition including a material of the gate electrode to form a gate electrode on the first liquid-repellent region of the substrate;

forming a gate insulating film to cover the gate electrode;

forming a semiconductor film over the gate electrode;

forming a semiconductor film having one conductivity over the semiconductor film;

performing a plasma treatment on the semiconductor film having one conductivity and the gate insulating film to form a second liquid-repellent region;

dropping a composition including a material of source and drain electrodes to form the source and drain electrodes on the second liquid-repellent region of the semiconductor film having one conductivity and the gate insulating film.

3. A method for manufacturing a thin film transistor comprising:

forming source and drain electrodes;

forming a semiconductor film over the source and drain electrodes;

performing a plasma treatment on a surface for forming a gate electrode over the semiconductor film to form a liquid-repellent region; and

dropping a composition including a material of the gate electrode to form the gate electrode on the liquid-repellent region of the surface for forming the gate electrode.

4. A method for manufacturing a thin film transistor comprising:

forming source and drain electrodes over a base film;

forming a semiconductor film over the source and drain electrodes;

performing a plasma treatment on a surface of the semiconductor film to form a first liquid-repellent region;

dropping a composition including a material of a mask to forming the mask on the first liquid-repellent region of the semiconductor film;

patterning the semiconductor film by using the mask; forming a gate insulating film to cover the semiconductor film;

performing a plasma treatment on the gate insulating film to form a second liquid-repellent region;

dropping a composition including a material of a gate electrode to form the gate electrode on the second liquid repellent region of the gate insulating film.

5. A method for manufacturing a thin film transistor comprising:

performing a plasma treatment on a base film to form a first liquid-repellent region;

dropping a composition including a material of source and drain electrodes to form the source and drain electrodes on the first liquid-repellent region of the base film;

forming a semiconductor film over the source and drain electrodes;

performing a plasma treatment on the semiconductor film to form a second liquid-repellent region;

dropping a composition including a material of a mask to forming the mask on the second liquid-repellent region of the semiconductor film;

patterning the semiconductor film by using the mask;

forming a gate insulating film to cover the semiconductor film;

performing a plasma treatment on the gate insulating film to form a third liquid-repellent region; and

dropping a composition including a material of a gate electrode to form the gate electrode on the third liquid-repellent region of the gate insulating film.

6. A method for manufacturing a thin film transistor comprising:

forming a Teflon film;

dropping a composition including a material of a gate electrode to form the gate electrode over the Teflon film;

performing a heat treatment so as to bake the gate electrode; and

removing the Teflon film by the heat treatment.

7. A method for manufacturing a thin film transistor comprising:

forming a first Teflon film;

dropping a composition including a material of a gate electrode to form the gate electrode over the first Teflon film;

performing a heat treatment so as to bake the gate electrode;

removing the first Teflon film by the heat treatment;

forming a gate insulating film to cover the gate electrode;

forming a semiconductor film over the gate electrode;

forming a semiconductor film having one conductivity over the semiconductor film;

forming a second Teflon film over the semiconductor film having one conductivity and the gate insulating film;

dropping a composition including a material of source and drain electrodes to form the source and drain electrodes over the semiconductor film having one conductivity and the gate insulating film;

performing a heat treatment so as to bake the source and drain electrodes; and

removing the second Teflon film by the heat treatment.

8. The method for manufacturing a thin film transistor according to any one of claims 1 , 2 , 3 , 4 , 5 , 6 , and 7 , comprising:

forming an interlayer insulating film over the thin film transistor;

forming an opening in the interlayer insulating film;

performing a plasma treatment on the interlayer insulating film in winch the opening is formed so that the opening and a surface of the interlayer insulating film become liquid-repellent; and

dropping a composition including a material of a wiring to form the wiring to be connected to the source or drain electrodes of the thin film transistor though the opening.

9. The method for manufacturing a thin film transistor according to any one of claims 1 , 2 , 3 , 4 , 5 , 6 , and 7 , comprising:

forming an interlayer insulating film over the thin film transistor;

performing a plasma treatment on the interlayer insulating film so that a surface of the interlayer insulating film become liquid-repellent;

forming an opening in the interlayer insulating film; and

dropping a composition including a material of a wiring to form the wiring to be connected to the source electrode or drain electrode of the thin film transistor through the opening;

wherein the opening is less liquid-repellent than the surface of the interlayer insulating film.

10. The method for forming a wiring according to any one of claims 1 , 2 , 3 , 4 , 5 , 6 , and 7 , wherein the composition is dropped by an ink-jetting method.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2005
From: MAEKAWA, SHINJI; MURANAKA, KOJI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 016192/0279 →
Priority Claims (1)
JP 2003-368030 · Oct 28, 2003 · national
Continuity (1)
Related Publication 20050112906A1 · May 26, 2005