IP Library Granted Patent US 7,226,844
Granted Patent B2
US 7,226,844 · App. 11/091,950 · Granted Jun 5, 2007

Method of manufacturing a bipolar transistor with a single-crystal base contact

Assignee: STMicroelectronics SA
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Quick Facts
Patent No.
US 7,226,844
App. No.
11/091,950
Granted
Jun 5, 2007
Kind
B2
Abstract

A method forms a bipolar transistor in a semiconductor substrate of a first conductivity type. The method includes: forming on the substrate a single-crystal silicon-germanium layer; forming a heavily-doped single-crystal silicon layer of a second conductivity type; forming a silicon oxide layer; opening a window in the silicon oxide and silicon layers; forming on the walls of the window a silicon nitride spacer; removing the silicon-germanium layer from the bottom of the window; forming in the cavity resulting from the previous removal a heavily-doped single-crystal semiconductor layer of the second conductivity type; and forming in said window the emitter of the transistor.

Claims (55)

1. A method for manufacturing a bipolar transistor in a semiconductor substrate of a first conductivity type, comprising the steps of:

forming on the substrate a single-crystal silicon-germanium layer;

forming a heavily-doped single-crystal silicon layer of a second conductivity type overlying the single-crystal silicon-germanium layer;

forming a silicon oxide layer overlying the single-crystal silicon layer;

opening a window in the silicon oxide and silicon layers, thereby exposing a portion of the silicon-germanium layer at bottom of the window;

forming on walls of the window a silicon nitride spacer;

removing the silicon-germanium layer from the bottom of the window to provide a cavity extending beyond the bottom of the window into areas under the silicon layer;

forming in the cavity a heavily-doped single-crystal semiconductor layer of the second conductivity type; and

forming in said window an emitter of the transistor.

2. The method of claim 1 , comprising the additional steps of:

locally opening at least the silicon oxide and silicon layers to expose the upper surface of the silicon-germanium layer;

at least partially removing the silicon-germanium layer to provide a recess extending beyond the opening and into areas under the silicon layer; and

depositing a silicon oxide layer to fill the recess.

3. The method of claim 2 , wherein said additional steps are implemented after the step of forming the single-crystal semiconductor layer.

4. The method of claim 2 , wherein said additional steps are implemented after the step of forming an emitter.

5. The method of claim 2 , wherein the step of removing the silicon-germanium layer is implemented to completely remove said silicon-germanium layer.

6. A method of manufacturing a bipolar transistor on a semiconductor substrate of a first conductivity type, comprising:

epitaxially growing a sacrificial semiconductor layer on the substrate;

epitaxially growing a first semiconductor layer of a second conductivity type on the sacrificial semiconductor layer;

removing a portion of the first semiconductor layer to provide a first opening;

thereby exposing a top surface of the sacrificial semiconductor layer;

selectively removing a portion of the sacrificial semiconductor layer to extend the

first opening to a top surface of the substrate and into areas under the first semiconductor layer;

epitaxially growing a second semiconductor layer of the second conductivity type on the substrate within the opening; and

forming an emitter overlying the second semiconductor layer.

7. The method of claim 6 wherein, the sacrificial semiconductor layer is a silicon-germanium layer, the first and second semiconductor layers are silicon layers.

8. The method of claim 6 wherein a portion of the first semiconductor layer not removed provides part of a base that includes the second semiconductor layer.

9. The method of claim 6 further comprising providing a spacer insulating the emitter from the first semiconductor layer.

10. The method of claim 6 further comprising:

removing a portion the first semiconductor layer to provide a second opening, thereby exposing a top surface of the sacrificial semiconductor layer;

selectively removing portions of the first semiconductor layer to extend the second opening to a top surface of the substrate and into areas under the first semiconductor layer, wherein the second opening and the first opening are separated by a portion of the first semiconductor layer; and

depositing an insulating layer in the second opening.

11. A method comprising:

providing a substrate of a single crystal semiconductor material;

forming a first semiconductor layer on the substrate, the first semiconductor layer having a top surface;

forming a second semiconductor layer on the top surface of the first semiconductor layer;

forming a dielectric layer on the second semiconductor layer;

selectively etching an opening in the dielectric layer and the second semiconductor layer, exposing a part of the top surface of the first semiconductor layer;

forming a cavity in the first semiconductor layer by selectively etching the first semiconductor layer, the cavity extending beyond the opening in the second semiconductor layer into a portion beneath the second semiconductor layer and exposing a partial surface of the substrate; and

filling the cavity by epitaxially growing a third semiconductor layer on the partial surface of the substrate, wherein the first semiconductor layer is a single crystal silicon-germanium layer.

12. The method of claim 11 wherein the opening in the dielectric layer and the second semiconductor layer is about 200 to about 1000 nm wide.

13. The method of claim 11 further comprising forming spacers on walls of the opening in the dielectric layer and the second semiconductor layer.

14. The method of claim 11 wherein the second semiconductor layer is a single crystal silicon layer.

15. The method of claim 11 wherein the second semiconductor layer and the third semiconductor layer have the same conductivity type.

16. The method of claim 11 wherein the third semiconductor layer forms a base of a bipolar transistor.

17. A method for manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, comprising the steps of:

forming on the single-crystal silicon substrate a single crystal silicon-germanium layer;

forming a single-crystal silicon layer of a second conductivity type on the single crystal silicon-germanium layer;

forming a dielectric layer overlying the single crystal silicon layer of the second conductivity type;

forming an opening through the dielectric layer and single-crystal silicon layer of the second conductivity type, the opening having a width and reaching a top surface of the silicon-germanium layer;

etching the silicon-germanium layer to provide a cavity in the silicon-germanium layer, the cavity extending beyond the width of the opening into areas under the single crystal silicon layer of the second conductivity type; and

forming in the cavity a single crystal semiconductor layer of the second conductivity type.

18. The method of claim 17 wherein forming the single crystal semiconductor layer comprises epitaxially growing on the single-crystal silicon substrate.

19. The method of claim 17 wherein the single crystal silicon-germanium layer comprises about 20% to 25% of germanium.

20. The method of claim 17 wherein forming the opening comprises selectively etching the dielectric layer and the single crystal silicon-germanium layer without etching the single crystal silicon layer.

Assignments (2)
CHANGE OF NAME Recorded Mar 26, 2024
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS FRANCE
Reel/Frame 066911/0286 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2005
From: CHANTRE, ALAIN; CHEVALIER, PASCAL
To: STMICROELECTRONICS SA
Reel/Frame 016072/0742 →
Priority Claims (1)
FR 04 50610 · Mar 29, 2004 · national
Continuity (1)
Related Publication 20050215021A1 · Sep 29, 2005